MC10EP51

更新时间： 2024-11-01 22:30:59

品牌	Logo	应用领域
安森美 - ONSEMI		触发器时钟
页数	文件大小	规格书
8页	79K
描述
3.3V / 5V ECL D Flip-Flop with Reset and Differential Clock

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数据手册

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MC10EP51 数据手册

MC10EP51, MC100EP51

3.3V / 5VĄECL D Flip-Flop

with Reset and Differential

Clock

The MC10/100EP51 is a differential clock D flip–flop with reset.

The device is functionally equivalent to the EL51 and LVEL51

devices.

The reset input is an asynchronous, level triggered signal. Data

enters the master portion of the flip–flop when the clock is LOW and is

transferred to the slave, and thus the outputs, upon a positive transition

of the clock. The differential clock inputs of the EP51 allow the device

to be used as a negative edge triggered flip-flop.

http://onsemi.com

MARKING DIAGRAMS*

HEP51

ALYW

KEP51

ALYW

SO–8

The differential input employs clamp circuitry to maintain stability

under open input conditions. When left open, the CLK input will be

D SUFFIX

CASE 751

pulled down to V and the CLK input will be biased at V /2.

The 100 Series contains temperature compensation.

• 350 ps Typical Propagation Delay

• Maximum Frequency > 3 GHz Typical

HP51

ALYW

KP51

ALYW

TSSOP–8

DT SUFFIX

CASE 948R

• PECL Mode Operating Range: V = 3.0 V to 5.5 V

with V = 0 V

• NECL Mode Operating Range: V = 0 V

L = Wafer Lot

Y = Year

H = MC10

K = MC100

with V = –3.0 V to –5.5 V

• Open Input Default State

• Safety Clamp on Inputs

W = Work Week

A = Assembly Location

*For additional information, see Application Note

AND8002/D

ORDERING INFORMATION

Device

Package

Shipping

MC10EP51D

SO–8

98 Units/Rail

MC10EP51DR2

MC100EP51D

MC100EP51DR2

MC10EP51DT

SO–8

2500 Tape & Reel

98 Units/Rail

SO–8

2500 Tape & Reel

100 Units/Rail

TSSOP–8

MC10EP51DTR2 TSSOP–8 2500 Tape & Reel

MC100EP51DT TSSOP–8 100 Units/Rail

MC100EP51DTR2 TSSOP–8 2500 Tape & Reel

Semiconductor Components Industries, LLC, 2001

Publication Order Number:

April, 2001 – Rev. 3

MC10EP51/D

12 3 4 5 6 7 8

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MC10EP51DTR2G	ONSEMI	获取价格	3.3V / 5V ECL D Flip−Flop with Reset and Differential Clock