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MC10EP446FAG PDF预览

MC10EP446FAG

更新时间: 2024-02-21 04:59:18
品牌 Logo 应用领域
安森美 - ONSEMI 转换器移位寄存器触发器逻辑集成电路
页数 文件大小 规格书
20页 269K
描述
3.3 V/5 V 8-Bit CMOS/ECL/TTL Data Input Parallel/Serial Converter

MC10EP446FAG 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:QFN
包装说明:VQCCN,针数:32
Reach Compliance Code:unknown风险等级:5.71
其他特性:ECL MODE: VCC = 0V WITH VEE = -3V TO -5.5V计数方向:RIGHT
系列:10EJESD-30 代码:S-PQCC-N32
JESD-609代码:e3长度:5 mm
逻辑集成电路类型:PARALLEL IN SERIAL OUT湿度敏感等级:NOT SPECIFIED
位数:8功能数量:1
端子数量:32最高工作温度:85 °C
最低工作温度:-40 °C输出极性:COMPLEMENTARY
封装主体材料:PLASTIC/EPOXY封装代码:VQCCN
封装形状:SQUARE封装形式:CHIP CARRIER, VERY THIN PROFILE
峰值回流温度(摄氏度):260传播延迟(tpd):1.025 ns
认证状态:COMMERCIAL座面最大高度:1 mm
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):3 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
技术:ECL温度等级:INDUSTRIAL
端子面层:MATTE TIN端子形式:NO LEAD
端子节距:0.5 mm端子位置:QUAD
处于峰值回流温度下的最长时间:40触发器类型:NEGATIVE EDGE
宽度:5 mm最小 fmax:3200 MHz
Base Number Matches:1

MC10EP446FAG 数据手册

 浏览型号MC10EP446FAG的Datasheet PDF文件第2页浏览型号MC10EP446FAG的Datasheet PDF文件第3页浏览型号MC10EP446FAG的Datasheet PDF文件第4页浏览型号MC10EP446FAG的Datasheet PDF文件第5页浏览型号MC10EP446FAG的Datasheet PDF文件第6页浏览型号MC10EP446FAG的Datasheet PDF文件第7页 
MC10EP446, MC100EP446  
3.3 V/5 V 8-Bit  
CMOS/ECL/TTL Data Input  
Parallel/Serial Converter  
Description  
http://onsemi.com  
The MC10/100EP446 is an integrated 8bit parallel to serial data  
converter. The device is designed with unique circuit topology to  
operate for NRZ data rates up to 3.2 Gb/s. The conversion sequence  
from parallel data into a serial data stream is from bit D0 to D7. The  
parallel input pins D0D7 are configurable to be threshold controlled by  
CMOS, ECL, or TTL level signals. The serial data rate output can be  
selected at internal clock data rate or twice the internal clock data rate  
using the CKSEL pin.  
Control pins are provided to reset (SYNC) and disable internal clock  
circuitry (CKEN). In either CKSEL modes, the internal flipflops are  
triggered on the rising edge for CLK and the multiplexers are switched  
on the falling edge of CLK, therefore, all associated specification  
limits are referenced to the negative edge of the clock input.  
MARKING DIAGRAMS*  
MCxxx  
EP446  
AWLYYWWG  
LQFP32  
FA SUFFIX  
CASE 873A  
Additionally, V pin is provided for singleended input condition.  
BB  
The 100 Series devices contain temperature compensation network.  
1
MCxxx  
EP446  
Features  
32  
1
AWLYYWWG  
3.2 Gb/s Typical Data Rate Capability  
Differential Clock and Serial Outputs  
QFN32  
MN SUFFIX  
CASE 488AM  
G
V Output for Single-ended Input Applications  
BB  
Asynchronous Data Reset (SYNC)  
PECL Mode Operating Range:  
xxx  
A
= 10 or 100  
= Assembly Location  
V
= 3.0 V to 5.5 V with V = 0 V  
EE  
WL, L = Wafer Lot  
YY, Y = Year  
CC  
NECL Mode Operating Range:  
= 0 V with V = 3.0 V to 5.5 V  
WW, W = Work Week  
V
CC  
EE  
G or G = PbFree Package  
Open Input Default State  
Safety Clamp on Inputs  
Parallel Interface Can Support PECL, TTL or CMOS  
PbFree Packages are Available*  
(Note: Microdot may be in either location)  
*For additional marking information, refer to  
Application Note AND8002/D.  
ORDERING INFORMATION  
See detailed ordering and shipping information in the package  
dimensions section on page 18 of this data sheet.  
*For additional information on our PbFree strategy and soldering details, please  
download the ON Semiconductor Soldering and Mounting Techniques  
Reference Manual, SOLDERRM/D.  
© Semiconductor Components Industries, LLC, 2007  
1
Publication Order Number:  
February, 2007 Rev. 9  
MC10EP446/D  

MC10EP446FAG 替代型号

型号 品牌 替代类型 描述 数据表
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