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MC10E175FN PDF预览

MC10E175FN

更新时间: 2024-02-04 14:25:06
品牌 Logo 应用领域
摩托罗拉 - MOTOROLA 触发器锁存器逻辑集成电路
页数 文件大小 规格书
4页 110K
描述
9-BIT LATCH WITH PARITY

MC10E175FN 技术参数

生命周期:Transferred零件包装代码:QLCC
包装说明:QCCJ, LDCC28,.5SQ针数:28
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.44Is Samacsys:N
其他特性:WITH PARITY GENERATION系列:10E
JESD-30 代码:S-PQCC-J28JESD-609代码:e0
长度:11.505 mm逻辑集成电路类型:D LATCH
位数:9功能数量:1
端子数量:28最高工作温度:85 °C
最低工作温度:输出特性:OPEN-EMITTER
输出极性:TRUE封装主体材料:PLASTIC/EPOXY
封装代码:QCCJ封装等效代码:LDCC28,.5SQ
封装形状:SQUARE封装形式:CHIP CARRIER
电源:-5.2 V最大电源电流(ICC):132 mA
Prop。Delay @ Nom-Sup:1.45 ns传播延迟(tpd):0.9 ns
认证状态:Not Qualified座面最大高度:4.57 mm
子类别:FF/Latches表面贴装:YES
技术:ECL温度等级:OTHER
端子面层:Tin/Lead (Sn/Pb)端子形式:J BEND
端子节距:1.27 mm端子位置:QUAD
触发器类型:LOW LEVEL宽度:11.505 mm
Base Number Matches:1

MC10E175FN 数据手册

 浏览型号MC10E175FN的Datasheet PDF文件第2页浏览型号MC10E175FN的Datasheet PDF文件第3页浏览型号MC10E175FN的Datasheet PDF文件第4页 
SEMICONDUCTOR TECHNICAL DATA  
The MC10E/100E175 is a 9-bit latch. It also features a tenth latched  
output, ODDPAR, which is formed as the odd parity of the nine data  
inputs (ODDPAR is HIGH if an odd number of the inputs are HIGH).  
The E175 can also be used to generate byte parity by using D8 as the  
parity-type select (L = even parity, H = odd parity), and using ODDPAR as  
the byte parity output.  
The LEN pin latches the data when asserted with a logical high and  
makes the latch transparent when placed at a logic low level.  
9-BIT LATCH  
WITH PARITY  
9-Bit Latch  
Parity Detection/Generation  
800ps Max. D to Output  
Reset  
Extended 100E V  
Range of – 4.2V to – 5.46V  
Internal 75kInput Pulldown Resistors  
EE  
Pinout: 28-Lead PLCC (Top View)  
FN SUFFIX  
PLASTIC PACKAGE  
CASE 776-02  
D
D
D
V
Q
Q
V
6
7
8
CCO  
22  
8
7
CCO  
25  
24  
23  
21  
20  
19  
Q
Q
V
18  
D
26  
6
5
17  
16  
15  
D
27  
28  
5
4
D
CC  
3
LOGIC DIAGRAM  
1
Q
V
4
EE  
2
3
4
14  
13  
Q
V
LEN  
MR  
D
0
Q
Q
Q
Q
0
3
D
EN  
CCO  
R
R
R
D
2
Q
2
12  
BITS  
1–7  
5
6
7
8
9
10  
11  
D
D
V
Q
V
Q
1
D
8
D
Q
8
1
0
CCO  
0
CCO  
EN  
* All V  
and V  
pins are tied together on the die.  
CC  
CCO  
PIN NAMES  
Pin  
D
ODDPAR  
Function  
EN  
D
– D  
LEN  
MR  
– Q  
ODDPAR  
Data Inputs  
0
8
Latch Enable  
Master Reset  
Data Outputs  
Parity Output  
LEN  
MR  
Q
0
8
12/93  
Motorola, Inc. 1996  
REV 2  

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