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MC10121_02 PDF预览

MC10121_02

更新时间: 2024-11-06 04:59:43
品牌 Logo 应用领域
安森美 - ONSEMI
页数 文件大小 规格书
8页 108K
描述
4-Wide OR-AND/OR-AND Gate

MC10121_02 数据手册

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MC10121  
4-Wide OR-AND/OR-AND  
Gate  
The MC10121 is a basic logic building block providing the  
simultaneous OR–AND/OR–AND–Invert function, useful in data  
control and digital multiplexing applications.  
http://onsemi.com  
P = 100 mW typ/pkg (No Load)  
D
t = 2.3 ns typ  
pd  
MARKING  
DIAGRAMS  
t , t = 2.5 ns typ (20%–80%)  
r
f
16  
LOGIC DIAGRAM  
CDIP–16  
L SUFFIX  
CASE 620  
MC10121L  
AWLYYWW  
4
5
6
7
9
1
16  
PDIP–16  
P SUFFIX  
CASE 648  
MC10121P  
AWLYYWW  
2
3
10  
1
1
11  
12  
13  
14  
15  
V
V
= PIN 1  
= PIN 16  
= PIN 8  
CC1  
PLCC–20  
FN SUFFIX  
CASE 775  
10121  
CC2  
V
EE  
AWLYYWW  
A
= Assembly Location  
WL = Wafer Lot  
YY = Year  
WW = Work Week  
DIP  
PIN ASSIGNMENT  
V
A
V
CC2  
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
11  
10  
9
CC1  
ORDERING INFORMATION  
A4  
IN  
IN  
IN  
IN  
OUT  
OUT  
Device  
Package  
Shipping  
A4  
A4  
A3  
A3  
A
MC10121L  
CDIP–16  
25 Units / Rail  
A1  
IN  
IN  
IN  
IN  
A1  
MC10121P  
PDIP–16  
PLCC–20  
25 Units / Rail  
46 Units / Rail  
A1  
A2  
V
IN  
MC10121FN  
A2 , A3  
IN  
IN  
A2  
IN  
EE  
Pin assignment is for Dual–in–Line Package.  
For PLCC pin assignment, see the Pin Conversion Tables on page 18  
of the ON Semiconductor MECL Data Book (DL122/D).  
Semiconductor Components Industries, LLC, 2002  
1
Publication Order Number:  
January, 2002 – Rev. 7  
MC10121/D  

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