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MC10124_02

更新时间: 2024-09-16 04:59:43
品牌 Logo 应用领域
安森美 - ONSEMI /
页数 文件大小 规格书
8页 121K
描述
Quad TTL to MECL Translator

MC10124_02 数据手册

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MC10124  
Quad TTL to MECL  
Translator  
The MC10124 is a quad translator for interfacing data and control  
signals between a saturated logic section and the MECL section of  
digital systems. The MC10124 has TTL compatible inputs, and  
MECL complementary open–emitter outputs that allow use as an  
inverting/ non–inverting translator or as a differential line driver.  
When the common strobe input is at the low logic level, it forces all  
true outputs to a MECL low logic state and all inverting outputs to a  
MECL high logic state.  
http://onsemi.com  
MARKING  
DIAGRAMS  
16  
Power supply requirements are ground, +5.0 Volts, and –5.2 Volts.  
Propagation delay of the MC10124 is typically 3.5 ns. The dc levels  
are standard or Schottky TTL in, MECL 10,000 out.  
CDIP–16  
L SUFFIX  
CASE 620  
MC10124L  
AWLYYWW  
1
An advantage of this device is that TTL level information can be  
transmitted differentially, via balanced twisted pair lines, to the MECL  
equipment, where the signal can be received by the MC10115 or  
MC10116 differential line receivers. The MC10124 is useful in  
computers, instrumentation, peripheral controllers, test equipment,  
and digital communications systems.  
16  
PDIP–16  
P SUFFIX  
CASE 648  
MC10124P  
AWLYYWW  
1
1
P = 380 mW typ/pkg (No Load)  
D
t = 3.5 ns typ (+ 1.5 Vdc in to 50% out)  
pd  
PLCC–20  
FN SUFFIX  
CASE 775  
10124  
t , t = 2.5 ns typ (20%–80%)  
r
f
AWLYYWW  
LOGIC DIAGRAM  
5
6
4
2
A
= Assembly Location  
7
10  
11  
3
1
WL = Wafer Lot  
YY = Year  
WW = Work Week  
12  
15  
ORDERING INFORMATION  
13  
14  
Device  
Package  
Shipping  
Gnd  
V
=
=
=
PIN 16  
(+5.0Vdc)  
(-5.2Vdc)  
PIN 9  
PIN 8  
MC10124L  
CDIP–16  
25 Units / Rail  
CC  
V
EE  
MC10124P  
PDIP–16  
PLCC–20  
25 Units / Rail  
46 Units / Rail  
DIP PIN ASSIGNMENT  
MC10124FN  
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
11  
10  
9
B
GND  
OUT  
OUT  
OUT  
OUT  
C
OUT  
A
B
A
D
D
C
D
C
V
OUT  
OUT  
OUT  
IN  
A
IN  
COMMON  
STROBE  
B
IN  
IN  
V
CC  
EE  
Pin assignment is for Dual–in–Line Package.  
For PLCC pin assignment, see the Pin Conversion Tables on page 18  
of the ON Semiconductor MECL Data Book (DL122/D).  
Semiconductor Components Industries, LLC, 2002  
1
Publication Order Number:  
January, 2002 – Rev. 7  
MC10124/D  

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