Datasheet > MC10129L

MC10129L

更新时间： 2024-11-18 20:32:07

品牌	Logo	应用领域
安森美 - ONSEMI		/
页数	文件大小	规格书
12页	173K
描述
QUAD LINE RECEIVER, CDIP16, CERAMIC, DIP-16

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技术参数
数据手册

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MC10129L 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
零件包装代码：	DIP	包装说明：	DIP,
针数：	16	Reach Compliance Code：	compliant
ECCN代码：	EAR99	HTS代码：	8542.39.00.01
风险等级：	5.92	输入特性：	SCHMITT TRIGGER
接口集成电路类型：	LINE RECEIVER	接口标准：	GENERAL PURPOSE
JESD-30 代码：	R-GDIP-T16	JESD-609代码：	e0
长度：	19.495 mm	标称负供电电压：	-5.2 V
功能数量：	4	端子数量：	16
最高工作温度：	85 °C	最低工作温度：	-30 °C
封装主体材料：	CERAMIC, GLASS-SEALED	封装代码：	DIP
封装形状：	RECTANGULAR	封装形式：	IN-LINE
峰值回流温度（摄氏度）：	NOT SPECIFIED	认证状态：	Not Qualified
最大接收延迟：	15 ns	接收器位数：	4
座面最大高度：	5.08 mm	标称供电电压：	5 V
表面贴装：	NO	技术：	ECL
温度等级：	OTHER	端子面层：	TIN LEAD
端子形式：	THROUGH-HOLE	端子节距：	2.54 mm
端子位置：	DUAL	处于峰值回流温度下的最长时间：	NOT SPECIFIED
宽度：	7.62 mm	Base Number Matches：	1

MC10129L 数据手册

The MC10129 data inputs are compatible with, and accept TTL

logic levels as well as levels compatible with IBM–type buses. The

clock, strobe, and reset inputs accept MECL 10,000 logic levels.

The data inputs accept the bus levels, and storage elements are

provided to yield temporary latch storage of the information after

receiving it from the bus. The outputs can be strobed to allow accurate

synchronization of signals and/or connection to MECL 10,000 level

buses. When the clock is low, and the reset input is disabled, the

outputs will follow the D inputs. The latches will store the data on the

rising edge of the clock. The outputs are enabled when the strobe input

http://onsemi.com

MARKING

DIAGRAMS

CDIP–16

L SUFFIX

CASE 620

is high. Unused D inputs must be tied to V

strobe, and reset inputs each have 50 k ohm pulldown resistors to V

They may be left floating, if not used.

or Gnd. The clock,

MC10129L

AWLYYWW

The MC10129 will operate in either of two modes. The first mode is

obtained by tying the hysteresis control input to V . In this mode, the

input threshold points of the D inputs are fixed. The second mode is

obtained by tying the hysteresis control input to ground. In this mode,

input hysteresis is achieved as shown in the test table. This hysteresis

is desirable where extra noise margin is required on the D inputs. The

outer input pins are unaffected by the mode of operation used.

The MC10129 is especially useful in interface applications for

central processors, mini–computers, and peripheral equipment.

PDIP–16

P SUFFIX

CASE 648

MC10129P

AWLYYWW

PLCC–20

FN SUFFIX

CASE 775

10129

AWLYYWW

• P = 750 mW typ/pkg (No Load)

• t = 10 ns typ

• V Max = 7.0 Vdc

= Assembly Location

WL = Wafer Lot

YY = Year

WW = Work Week

ORDERING INFORMATION

Device

Package

Shipping

MC10129L

CDIP–16

25 Units / Rail

MC10129P

PDIP–16

PLCC–20

25 Units / Rail

46 Units / Rail

MC10129FN

Semiconductor Components Industries, LLC, 2000

Publication Order Number:

March, 2000 – Rev. 7

MC10129/D

12 3 4 5 6 7...12

中文翻译

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与MC10129L相关器件

型号	品牌	获取价格	描述	数据表
MC10129LDS	MOTOROLA	获取价格	TTL to ECL Translator, ECL10K, CDIP16
MC10129P	MOTOROLA	获取价格	暂无描述
MC10129P	ONSEMI	获取价格	QUAD LINE RECEIVER, PDIP16, PLASTIC, DIP-16
MC10129PD	MOTOROLA	获取价格	TTL to ECL Translator, ECL10K, PDIP16
MC10129PDS	MOTOROLA	获取价格	TTL to ECL Translator, ECL10K, PDIP16
MC10129PS	MOTOROLA	获取价格	TTL to ECL Translator, ECL10K, PDIP16
MC10130	MOTOROLA	获取价格	DUAL LATCH
MC10130F	MOTOROLA	获取价格	暂无描述
MC10130FN	MOTOROLA	获取价格	10K SERIES, DUAL LOW LEVEL TRIGGERED D LATCH, COMPLEMENTARY OUTPUT, PQCC20, PLASTIC, LCC-2
MC10130FNR2	MOTOROLA	获取价格	10K SERIES, DUAL LOW LEVEL TRIGGERED D LATCH, COMPLEMENTARY OUTPUT, PQCC20, PLASTIC, LCC-2

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