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MC10131P PDF预览

MC10131P

更新时间: 2024-11-04 04:59:43
品牌 Logo 应用领域
安森美 - ONSEMI 触发器锁存器逻辑集成电路光电二极管
页数 文件大小 规格书
8页 113K
描述
Dual Type D Master-Slave Flip-Flop

MC10131P 技术参数

是否Rohs认证:不符合生命周期:Obsolete
零件包装代码:DIP包装说明:DIP-16
针数:16Reach Compliance Code:not_compliant
HTS代码:8542.39.00.01风险等级:5.15
Is Samacsys:N其他特性:WITH ADDITIONAL COMMON CLOCK
系列:10KJESD-30 代码:R-PDIP-T16
JESD-609代码:e0长度:19.175 mm
逻辑集成电路类型:D FLIP-FLOP最大频率@ Nom-Sup:125000000 Hz
位数:1功能数量:2
端子数量:16最高工作温度:85 °C
最低工作温度:-30 °C输出特性:OPEN-EMITTER
输出极性:COMPLEMENTARY封装主体材料:PLASTIC/EPOXY
封装代码:DIP封装等效代码:DIP16,.3
封装形状:RECTANGULAR封装形式:IN-LINE
峰值回流温度(摄氏度):NOT SPECIFIED电源:-5.2 V
最大电源电流(ICC):62 mA传播延迟(tpd):4.5 ns
认证状态:Not Qualified座面最大高度:4.44 mm
子类别:FF/Latches表面贴装:NO
技术:ECL温度等级:OTHER
端子面层:Tin/Lead (Sn80Pb20)端子形式:THROUGH-HOLE
端子节距:2.54 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED触发器类型:POSITIVE EDGE
宽度:7.62 mm最小 fmax:125 MHz
Base Number Matches:1

MC10131P 数据手册

 浏览型号MC10131P的Datasheet PDF文件第2页浏览型号MC10131P的Datasheet PDF文件第3页浏览型号MC10131P的Datasheet PDF文件第4页浏览型号MC10131P的Datasheet PDF文件第5页浏览型号MC10131P的Datasheet PDF文件第6页浏览型号MC10131P的Datasheet PDF文件第7页 
MC10131  
Dual Type D Master-Slave  
Flip-Flop  
The MC10131 is a dual master–slave type D flip–flop.  
Asynchronous Set (S) and Reset (R) override Clock (C ) and Clock  
C
Enable (C ) inputs. Each flip–flop may be clocked separately by  
E
http://onsemi.com  
holding the common clock in the low state and using the enable inputs  
for the clocking function. If the common clock is to be used to clock  
the flip–flop, the Clock Enable inputs must be in the low state. In this  
case, the enable inputs perform the function of controlling the  
common clock.  
The output states of the flip–flop change on the positive transition of  
the clock. A change in the information present at the data (D) input  
will not affect the output information at any other time due to master  
slave construction.  
MARKING  
DIAGRAMS  
16  
CDIP–16  
L SUFFIX  
CASE 620  
MC10131L  
AWLYYWW  
1
16  
P = 235 mW typ/pkg (No Load)  
D
PDIP–16  
P SUFFIX  
CASE 648  
MC10131P  
AWLYYWW  
F = 160 MHz typ  
Tog  
t = 3.0 ns typ  
pd  
1
t , t = 2.5 ns typ (20%–80%)  
1
r
f
DIP PIN ASSIGNMENT  
PLCC–20  
FN SUFFIX  
CASE 775  
10131  
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
11  
10  
9
V
CC1  
V
CC2  
AWLYYWW  
Q1  
Q2  
Q2  
R2  
S2  
Q1  
R1  
S1  
A
= Assembly Location  
WL = Wafer Lot  
YY = Year  
WW = Work Week  
C
E1  
C
E2  
D2  
CLOCKED TRUTH TABLE  
D1  
C
D
Q
n+1  
C
V
EE  
C
L
H
H
X
L
Q
n
Pin assignment is for Dual–in–Line Package.  
For PLCC pin assignment, see the Pin Conversion Tables on page 18  
of the ON Semiconductor MECL Data Book (DL122/D).  
L
H
H
LOGIC DIAGRAM  
C = C + C A clock H is a clock transition from a low to a  
E
C.  
S1  
D1  
5
high state.  
R–S TRUTH TABLE  
S
7
6
2
3
Q1  
Q1  
R
Q
n+1  
C
E1  
L
L
L
H
L
Q
n
H
R1  
4
9
H
H
L
C
C
H
N.D.  
R2 13  
N.D. = Not Defined  
14  
15  
Q2  
Q2  
C
11  
E2  
ORDERING INFORMATION  
D2 10  
Device  
Package  
Shipping  
S2 12  
MC10131L  
CDIP–16  
25 Units / Rail  
V
V
= PIN 1  
= PIN 16  
= PIN 8  
CC1  
MC10131P  
PDIP–16  
PLCC–20  
25 Units / Rail  
46 Units / Rail  
CC2  
V
MC10131FN  
EE  
Semiconductor Components Industries, LLC, 2002  
1
Publication Order Number:  
January, 2002 – Rev. 7  
MC10131/D  

MC10131P 替代型号

型号 品牌 替代类型 描述 数据表
MC10131L ONSEMI

完全替代

Dual Type D Master-Slave Flip-Flop
MC10H131PG ONSEMI

功能相似

Dual D Type Master−Slave Flip−Flop
MC10H131L ONSEMI

功能相似

Dual D Type Master−Slave Flip−Flop

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