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MC10125P PDF预览

MC10125P

更新时间: 2024-11-20 22:54:59
品牌 Logo 应用领域
摩托罗拉 - MOTOROLA 晶体转换器电平转换器驱动程序和接口锁存器接口集成电路晶体管光电二极管
页数 文件大小 规格书
7页 131K
描述
Quad MECL to TTL Transistor

MC10125P 技术参数

是否Rohs认证:不符合生命周期:Transferred
包装说明:PLASTIC, DIP-16Reach Compliance Code:unknown
ECCN代码:EAR99HTS代码:8542.39.00.01
风险等级:5.66Is Samacsys:N
最大延迟:6 ns输入特性:DIFFERENTIAL
接口集成电路类型:ECL TO TTL TRANSLATORJESD-30 代码:R-PDIP-T16
JESD-609代码:e0长度:19.175 mm
位数:1功能数量:4
端子数量:16最高工作温度:85 °C
最低工作温度:-30 °C输出特性:TOTEM-POLE
输出锁存器或寄存器:NONE输出极性:TRUE
封装主体材料:PLASTIC/EPOXY封装代码:DIP
封装等效代码:DIP16,.3封装形状:RECTANGULAR
封装形式:IN-LINE电源:5,-5.2 V
认证状态:Not Qualified座面最大高度:4.44 mm
子类别:Level Translators表面贴装:NO
技术:BIPOLAR温度等级:OTHER
端子面层:Tin/Lead (Sn/Pb)端子形式:THROUGH-HOLE
端子节距:2.54 mm端子位置:DUAL
宽度:7.62 mmBase Number Matches:1

MC10125P 数据手册

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SEMICONDUCTOR TECHNICAL DATA  
The MC10125 is a quad translator for interfacing data and control signals  
between the MECL section and saturated logic sections of digital systems. The  
MC10125 incorporates differential inputs and Schottky TTL “totem pole”  
outputs. Differential inputs allow for use as an inverting/ non–inverting translator  
or as a differential line receiver. The V  
reference voltage is available on pin 1  
BB  
for use in single–ended input biasing. The outputs of the MC10125 go to a low  
logic level whenever the inputs are left floating.  
L SUFFIX  
CERAMIC PACKAGE  
CASE 620–10  
Power supply requirements are ground, +5.0 Volts and –5.2 Volts.  
Propagation delay of the MC10125 is typically 4.5 ns. The MC10125 has fanout  
of 10 TTL loads. The dc levels are MECL 10,000 in and Schottky TTL, or TTL  
out. This device has an input common mode noise rejection of ± 1.0 Volt.  
An advantage of this device is that MECL level information can be received,  
via balanced twisted pair lines, in the TTL equipment. This isolates the MECL  
logic from the noisy TTL environment. This device is useful in computers,  
instrumentation, peripheral controllers, test equipment and digital  
communications systems.  
P SUFFIX  
PLASTIC PACKAGE  
CASE 648–08  
FN SUFFIX  
PLCC  
CASE 775–02  
P
= 380 mW typ/pkg (No Load)  
= 4.5 ns typ (50% to + 1.5 Vdc out)  
D
DIP  
t
pd  
PIN ASSIGNMENT  
t , t = 2.5 ns typ (1.0 V to 2.0 V)  
r f  
V
GND  
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
11  
10  
9
BB  
D
A
IN  
IN  
LOGIC DIAGRAM  
D
A
IN  
IN  
2
3
4
D
A
B
OUT  
OUT  
C
C
C
V
6
7
OUT  
IN  
OUT  
5
B
IN  
10  
11  
12  
B
IN  
IN  
V
EE  
CC  
14  
15  
13  
1
Pin assignment is for Dual–in–Line Package.  
For PLCC pin assignment, see the Pin Conversion  
Tables on page 6–11 of the Motorola MECL Data  
Book (DL122/D).  
V
*
BB  
Gnd  
=
=
=
PIN 16  
PIN 9  
PIN 8  
V
V
(+5.0Vdc)  
(–5.2Vdc)  
CC  
EE  
*V  
to be used to supply bias to the MC10125 only and bypassed (when used)  
with 0.01 µF to 0.1 µF capacitor to ground (0 V). V can source < 1.0 mA.  
BB  
BB  
When the input pin with the bubble goes positive, the output goes negative.  
3/93  
Motorola, Inc. 1996  
REV 5  

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