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MC10124 PDF预览

MC10124

更新时间: 2024-11-20 22:54:59
品牌 Logo 应用领域
安森美 - ONSEMI /
页数 文件大小 规格书
7页 129K
描述
Quad TTL to MECL Translator

MC10124 数据手册

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SEMICONDUCTOR TECHNICAL DATA  
The MC10124 is a quad translator for interfacing data and control signals  
between a saturated logic section and the MECL section of digital systems. The  
MC10124 has TTL compatible inputs, and MECL complementary open–emitter  
outputs that allow use as an inverting/ non–inverting translator or as a  
differential line driver. When the common strobe input is at the low logic level, it  
forces all true outputs to a MECL low logic state and all inverting outputs to a  
MECL high logic state.  
Power supply requirements are ground, +5.0 Volts, and –5.2 Volts.  
Propagation delay of the MC10124 is typically 3.5 ns. The dc levels are  
standard or Schottky TTL in, MECL 10,000 out.  
L SUFFIX  
CERAMIC PACKAGE  
CASE 620–10  
An advantage of this device is that TTL level information can be transmitted  
differentially, via balanced twisted pair lines, to the MECL equipment, where the  
signal can be received by the MC10115 or MC10116 differential line receivers.  
The MC10124 is useful in computers, instrumentation, peripheral controllers,  
test equipment, and digital communications systems.  
P SUFFIX  
PLASTIC PACKAGE  
CASE 648–08  
FN SUFFIX  
PLCC  
CASE 775–02  
P
= 380 mW typ/pkg (No Load)  
= 3.5 ns typ (+ 1.5 Vdc in to 50% out)  
D
t
pd  
t , t = 2.5 ns typ (20%–80%)  
r f  
DIP  
PIN ASSIGNMENT  
B
A
B
A
GND  
C
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
11  
10  
9
OUT  
OUT  
OUT  
OUT  
OUT  
LOGIC DIAGRAM  
D
D
C
OUT  
OUT  
OUT  
5
6
4
2
A
IN  
COMMON  
STROBE  
D
C
V
IN  
7
10  
11  
3
1
B
IN  
IN  
V
CC  
EE  
12  
15  
Pin assignment is for Dual–in–Line Package.  
For PLCC pin assignment, see the Pin Conversion  
Tables on page 6–11 of the Motorola MECL Data  
Book (DL122/D).  
13  
14  
Gnd  
=
=
=
PIN 16  
PIN 9  
PIN 8  
V
V
(+5.0Vdc)  
(–5.2Vdc)  
CC  
EE  
3/93  
Motorola, Inc. 1996  
REV 5  

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