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MC10123LD PDF预览

MC10123LD

更新时间: 2024-11-18 13:11:15
品牌 Logo 应用领域
摩托罗拉 - MOTOROLA 总线驱动器总线收发器逻辑集成电路输入元件
页数 文件大小 规格书
4页 106K
描述
Bus Driver, ECL10K, CDIP16

MC10123LD 技术参数

是否Rohs认证:不符合生命周期:Obsolete
包装说明:DIP, DIP16,.3Reach Compliance Code:unknown
风险等级:5.92Is Samacsys:N
JESD-30 代码:R-XDIP-T16JESD-609代码:e0
逻辑集成电路类型:BUS DRIVER端子数量:16
最高工作温度:85 °C最低工作温度:-30 °C
封装主体材料:CERAMIC封装代码:DIP
封装等效代码:DIP16,.3封装形状:RECTANGULAR
封装形式:IN-LINE电源:-5.2 V
子类别:Bus Driver/Transceivers表面贴装:NO
技术:ECL10K温度等级:OTHER
端子面层:Tin/Lead (Sn/Pb)端子形式:THROUGH-HOLE
端子节距:2.54 mm端子位置:DUAL
Base Number Matches:1

MC10123LD 数据手册

 浏览型号MC10123LD的Datasheet PDF文件第2页浏览型号MC10123LD的Datasheet PDF文件第3页浏览型号MC10123LD的Datasheet PDF文件第4页 
SEMICONDUCTOR TECHNICAL DATA  
The MC10123 consists of three NOR gates designed for bus driving  
applications on card or between cards. Output low logic levels are specified with  
V
= –2.1 Vdc so that the bus may be terminated to –2.0 Vdc. The gate output,  
OL  
when low, appears as a high impedance to the bus, because the output emitter–  
followers of the MC10123 are “turned–off.” This eliminates discontinuities in the  
characteristic impedance of the bus.  
The V  
level is specified when driving a 25–ohm load terminated to –2.0  
OH  
L SUFFIX  
CERAMIC PACKAGE  
CASE 620–10  
Vdc, the equivalent of a 50–ohm bus terminated at both ends. Although 25  
ohms is the lowest characteristic impedance that can be driven by the  
MC10123, higher impedance values may be used with this part. A typical  
50–ohm bus is shown in Figure 1.  
P SUFFIX  
PLASTIC PACKAGE  
CASE 648–08  
P
= 310 mW typ/pkg (No Load)  
= 3.0 ns typ  
D
t
pd  
FN SUFFIX  
PLCC  
CASE 775–02  
t , t = 2.5 ns typ (20%–80%)  
r f  
LOGIC DIAGRAM  
DIP  
4
5
PIN ASSIGNMENT  
3
6
7
V
B
V
CC2  
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
11  
10  
9
CC1  
9
10  
11  
C
C
C
C
OUT  
IN  
OUT  
OUT  
2
A
12  
13  
14  
A
IN  
IN  
15  
A
IN  
IN  
V
V
V
= PIN 1  
= PIN 16  
= PIN 8  
B
A
CC1  
CC2  
EE  
IN  
IN  
IN  
IN  
B
B
A
IN  
V
EE  
FIGURE 1 — 50–OHM BUS DRIVER (TYPICAL APPLICATION)  
Pin assignment is for Dual–in–Line Package.  
For PLCC pin assignment, see the Pin Conversion  
Tables on page 6–11 of the Motorola MECL Data  
Book (DL122/D).  
1/3 MC10123  
1/3 MC10123  
1/3 MC10123  
Z
= 50  
O
50  
50  
RECEIVERS (MECL GATES)  
–2.0  
VDC  
–2.0  
VDC  
3/93  
Motorola, Inc. 1996  
REV 5  

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