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MC-458CB64ESB-A10B PDF预览

MC-458CB64ESB-A10B

更新时间: 2024-11-02 11:11:15
品牌 Logo 应用领域
尔必达 - ELPIDA 存储内存集成电路动态存储器时钟
页数 文件大小 规格书
16页 135K
描述
8M-WORD BY 64-BIT SYNCHRONOUS DYNAMIC RAM MODULE (SO DIMM)

MC-458CB64ESB-A10B 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:MODULE包装说明:DIMM, DIMM144,32
针数:144Reach Compliance Code:unknown
ECCN代码:EAR99HTS代码:8542.32.00.28
风险等级:5.92Is Samacsys:N
访问模式:SINGLE BANK PAGE BURST最长访问时间:7 ns
其他特性:AUTO/SELF REFRESH最大时钟频率 (fCLK):100 MHz
I/O 类型:COMMONJESD-30 代码:R-XDMA-N144
内存密度:536870912 bit内存集成电路类型:SYNCHRONOUS DRAM MODULE
内存宽度:64湿度敏感等级:1
功能数量:1端口数量:1
端子数量:144字数:8388608 words
字数代码:8000000工作模式:SYNCHRONOUS
最高工作温度:70 °C最低工作温度:
组织:8MX64输出特性:3-STATE
封装主体材料:UNSPECIFIED封装代码:DIMM
封装等效代码:DIMM144,32封装形状:RECTANGULAR
封装形式:MICROELECTRONIC ASSEMBLY峰值回流温度(摄氏度):225
电源:3.3 V认证状态:Not Qualified
刷新周期:4096座面最大高度:25.4 mm
自我刷新:YES最大待机电流:0.004 A
子类别:DRAMs最大压摆率:0.88 mA
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):3 V
标称供电电压 (Vsup):3.3 V表面贴装:NO
技术:CMOS温度等级:COMMERCIAL
端子形式:NO LEAD端子节距:0.8 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
Base Number Matches:1

MC-458CB64ESB-A10B 数据手册

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DATA SHEET  
MOS INTEGRATED CIRCUIT  
MC-458CB64ESB, 458CB64PSB  
8M-WORD BY 64-BIT  
SYNCHRONOUS DYNAMIC RAM MODULE (SO DIMM)  
Description  
The MC-458CB64ESB and MC-458CB64PSB are 8,388,608 words by 64 bits synchronous dynamic RAM module  
(Small Outline DIMM) on which 4 pieces of 128M SDRAM: µPD45128163 are assembled.  
These modules provide high density and large quantities of memory in a small space without utilizing the surface-  
mounting technology on the printed circuit board.  
Decoupling capacitors are mounted on power supply line for noise reduction.  
Features  
8,388,608 words by 64 bits organization  
Clock frequency and access time from CLK  
Part number  
/CAS Latency  
Clock frequency  
(MAX.)  
Access time from CLK  
(MIN.)  
MC-458CB64ESB-A10B  
CL = 3  
CL = 2  
CL = 3  
CL = 2  
100 MHz  
67 MHz  
100 MHz  
67 MHz  
7 ns  
8 ns  
7 ns  
8 ns  
MC-458CB64PSB-A10B  
Fully Synchronous Dynamic RAM, with all signals referenced to a positive clock edge  
Pulsed interface  
Possible to assert random column address in every cycle  
Quad internal banks controlled by BA0 and BA1 (Bank Select)  
Programmable burst-length (1, 2, 4, 8 and Full Page)  
Programmable wrap sequence (Sequential / Interleave)  
Programmable /CAS latency (2, 3)  
Automatic precharge and controlled precharge  
CBR (Auto) refresh and self refresh  
Single +3.3 V ± 0.3 V power supply  
LVTTL compatible  
4,096 refresh cycles/64 ms  
Burst termination by Burst Stop command and Precharge command  
144-pin small outline dual in-line memory module (Pin pitch = 0.8 mm)  
Unbuffered type  
Serial PD  
The information in this document is subject to change without notice. Before using this document, please  
confirm that this is the latest version.  
Not all devices/types available in every country. Please check with local Elpida Memory, Inc. for  
availability and additional information.  
Document No. E0068N10 (1st edition)  
This product became EOL in September, 2002.  
(Previous No. M12263EJAV0DS00)  
Date Published January 2001 CP (K)  
Printed in Japan  
Elpida Memory, Inc. is a joint venture DRAM company of NEC Corporation and Hitachi, Ltd.  

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