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MC-45D16CD641KS-C80 PDF预览

MC-45D16CD641KS-C80

更新时间: 2024-11-26 11:11:15
品牌 Logo 应用领域
尔必达 - ELPIDA 存储内存集成电路动态存储器双倍数据速率时钟
页数 文件大小 规格书
14页 172K
描述
16 M-WORD BY 64-BIT DDR SYNCHRONOUS DYNAMIC RAM MODULE (SO DIMM)

MC-45D16CD641KS-C80 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:MODULE包装说明:DIMM, DIMM200,24
针数:200Reach Compliance Code:unknown
ECCN代码:EAR99HTS代码:8542.32.00.32
风险等级:5.92Is Samacsys:N
访问模式:DUAL BANK PAGE BURST最长访问时间:0.8 ns
其他特性:AUTO/SELF REFRESH最大时钟频率 (fCLK):125 MHz
I/O 类型:COMMONJESD-30 代码:R-XDMA-N200
内存密度:1073741824 bit内存集成电路类型:DDR DRAM MODULE
内存宽度:64功能数量:1
端口数量:1端子数量:200
字数:16777216 words字数代码:16000000
工作模式:SYNCHRONOUS最高工作温度:70 °C
最低工作温度:组织:16MX64
输出特性:3-STATE封装主体材料:UNSPECIFIED
封装代码:DIMM封装等效代码:DIMM200,24
封装形状:RECTANGULAR封装形式:MICROELECTRONIC ASSEMBLY
电源:2.5 V认证状态:Not Qualified
刷新周期:4096自我刷新:YES
最大待机电流:0.08 A子类别:DRAMs
最大压摆率:1.28 mA最大供电电压 (Vsup):2.7 V
最小供电电压 (Vsup):2.3 V标称供电电压 (Vsup):2.5 V
表面贴装:NO技术:MOS
温度等级:COMMERCIAL端子形式:NO LEAD
端子节距:0.6 mm端子位置:DUAL
Base Number Matches:1

MC-45D16CD641KS-C80 数据手册

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PRELIMINARY DATA SHEET  
MOS INTEGRATED CIRCUIT  
MC-45D16CD641KS  
16 M-WORD BY 64-BIT DDR SYNCHRONOUS DYNAMIC RAM MODULE  
(SO DIMM)  
Description  
The MC-45D16CD641KS is a 16,777,216 words by 64 bits DDR synchronous dynamic RAM module on which 8  
pieces of 128M DDR SDRAM: µPD45D128164 are assembled.  
These modules provide high density and large quantities of memory in a small space without utilizing the surface-  
mounting technology on the printed circuit board.  
Decoupling capacitors are mounted on power supply line for noise reduction.  
Features  
16,777,216 words by 64 bits organization  
Clock frequency  
Part number  
MC-45D16CD641KS-C75  
MC-45D16CD641KS-C80  
/CAS latency  
Clock frequency  
(MAX.)  
Module type  
CL = 2.5  
CL = 2  
133 MHz  
100 MHz  
125 MHz  
100 MHz  
DDR SDRAM  
SO DIMM  
CL = 2.5  
CL = 2  
Design specification  
Rev.1.0 compliant  
Fully Synchronous Dynamic RAM with all signals except DM, DQS and DQ referenced to a positive clock edge  
Double Data Rate interface  
Differential CLK (/CLK) input  
Data inputs and DM are synchronized with both edges of DQS  
Data outputs and DQS are synchronized with a cross point of CLK and /CLK  
Quad internal banks operation  
Possible to assert random column address in every clock cycle  
Programmable Mode register set  
/CAS latency (2, 2.5)  
Burst length (2, 4, 8)  
Wrap sequence (Sequential / Interleave)  
Automatic precharge and controlled precharge  
CBR (Auto) refresh and self refresh  
2.5 V ± 0.2 V Power supply for VDD  
2.5 V ± 0.2 V Power supply for VDDQ  
SSTL_2 compatible with all signals  
4,096 refresh cycles / 64 ms  
Burst termination by Precharge command and Burst stop command  
200-pin dual in-line memory module (Pin pitch = 0.6 mm)  
Unbuffered type  
Serial PD  
The information in this document is subject to change without notice. Before using this document, please  
confirm that this is the latest version.  
Not all devices/types available in every country. Please check with local Elpida Memory, Inc. for  
availability and additional information.  
Document No. E0187N10 (Ver. 1.0)  
Date Published August 2001 (K)  
Printed in Japan  
C
Elpida Memory, Inc. 2001  
Elpida Memory, Inc. is a joint venture DRAM company of NEC Corporation and Hitachi, Ltd.  

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