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M74HC40103M1R

更新时间： 2024-11-24 22:57:55
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 计数器
页数 文件大小 规格书
14页 302K
描述
8 STAGE PRESETTABLE SYNCHRONOUS DOWN COUNTERS

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中文翻译

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M74HC40103M1R 技术参数

是否Rohs认证： 符合生命周期：Obsolete
零件包装代码：SOIC包装说明：SOP, SOP16,.25
针数：16Reach Compliance Code：compliant
HTS代码：8542.39.00.01风险等级：5.83
其他特性：TCO OUTPUT; RESET TO MAX COUNT计数方向：DOWN
系列：HC/UHJESD-30 代码：R-PDSO-G16
JESD-609代码：e4长度：9.9 mm
负载电容（CL）：50 pF负载/预设输入：YES
逻辑集成电路类型：BINARY COUNTER最大频率@ Nom-Sup：13000000 Hz
最大I（ol）：0.004 A工作模式：SYNCHRONOUS
湿度敏感等级：1位数：8
功能数量：1端子数量：16
最高工作温度：125 °C最低工作温度：-55 °C
封装主体材料：PLASTIC/EPOXY封装代码：SOP
封装等效代码：SOP16,.25封装形状：RECTANGULAR
封装形式：SMALL OUTLINE包装方法：TUBE
峰值回流温度（摄氏度）：260电源：2/6 V
传播延迟（tpd）：280 ns认证状态：Not Qualified
座面最大高度：1.75 mm子类别：Counters
最大供电电压 (Vsup)：6 V最小供电电压 (Vsup)：2 V
标称供电电压 (Vsup)：4.5 V表面贴装：YES
技术：CMOS温度等级：MILITARY
端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)端子形式：GULL WING
端子节距：1.27 mm端子位置：DUAL
处于峰值回流温度下的最长时间：NOT SPECIFIED触发器类型：POSITIVE EDGE
宽度：3.9 mm最小 fmax：15 MHz
Base Number Matches：1

M74HC40103M1R 数据手册

 浏览型号M74HC40103M1R的Datasheet PDF文件第2页浏览型号M74HC40103M1R的Datasheet PDF文件第3页浏览型号M74HC40103M1R的Datasheet PDF文件第4页浏览型号M74HC40103M1R的Datasheet PDF文件第5页浏览型号M74HC40103M1R的Datasheet PDF文件第6页浏览型号M74HC40103M1R的Datasheet PDF文件第7页 
M54/74HC40102  
M54/74HC40103  
8 STAGE PRESETTABLE SYNCHRONOUS DOWN COUNTERS  
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HIGH SPEED  
fMAX = 40 MHz (TYP.) at VCC = 5 V  
LOW POWER DISSIPATION  
ICC = 4 µA (MAX.) at TA = 25 °C  
HIGH NOISE IMMUNITY  
VNIH = VNIL = 28 % VCC (MIN.)  
OUTPUT DRIVE CAPABILITY  
10 LSTTL LOADS  
SYMMETRICAL OUTPUT IMPEDANCE  
|IOH| = IOL = 4 mA (MIN.)  
BALANCED PROPAGATION DELAYS  
tPLH = tPHL  
B1R  
(Plastic Package)  
F1R  
(Ceramic Package)  
WIDE OPERATING VOLTAGE RANGE  
VCC (OPR) = 2 V to 6 V  
PIN AND FUNCTION COMPATIBLE WITH  
40102B/40103B  
M1R  
(Micro Package)  
C1R  
(Chip Carrier)  
ORDER CODES :  
M54HCXXXXXF1R M74HCXXXXXM1R  
M74HCXXXXXB1R M74HCXXXXX C1R  
DESCRIPTION  
PIN CONNECTIONS (top view)  
The M54/74HC40102/40103 are highspeed CMOS  
8-STAGE PRESETTABLE  
SYNCHRONOUS  
DOWN COUNTERS fabricated with silicon gate  
C2MOS technology. They achieve the high speed  
operation similar to equivalent LSTTL while main-  
taining the CMOS low power dissipation.  
The HC40102, and HC40103 consist of an 8-stage  
synchronous down counter with a single output  
which is active when the internal count is zero. The  
HC40102 is configured as two cascaded 4-bit BCD  
counters, and the HC40103 contains a single 8-bit  
binary counter. Each type has control inputs for en-  
abling or disabling the clock, for clearing the counter  
to its maximum count, and for presetting the counter  
either synchronously or asynchronously. All control  
inputs and the CARRY-OUT/ZERO-DETECT out-  
put are active-low logic. In normal operation, the  
counter is decremented by one count on each posi-  
tive transition of the CLOCK. Counting is inhibited  
when the CARRY-IN/COUNTER ENABLE (CI/CE)  
input is high. The CARRY-OUT/ZERO-DETECT  
(CO/ZD) output goes low when the count reaches  
zero if the CI/CE input is low, and remains low for  
one full clock period. When the SYNCHRONOUS  
PRESET-ENABLE (SPE) input is low, data at the J  
input is clocked into the counter on the next positive  
clock transition regardless of the state of the CI/CE  
input.  
NC =  
No Internal  
Connection  
March 1993  
1/14  
1234567...14

中文翻译

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