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M74HC4020TTR PDF预览

M74HC4020TTR

更新时间: 2024-11-25 22:52:59
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 计数器
页数 文件大小 规格书
11页 366K
描述
14 STAGE BINARY COUNTER

M74HC4020TTR 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Obsolete零件包装代码:TSSOP
包装说明:TSSOP, TSSOP16,.25针数:16
Reach Compliance Code:not_compliantHTS代码:8542.39.00.01
风险等级:5.34其他特性:OUTPUTS FROM 12 STAGES AVAILABLE
计数方向:UP系列:HC/UH
JESD-30 代码:R-PDSO-G16JESD-609代码:e0
长度:5 mm负载电容(CL):50 pF
负载/预设输入:NO逻辑集成电路类型:BINARY COUNTER
最大频率@ Nom-Sup:20000000 Hz最大I(ol):0.004 A
工作模式:ASYNCHRONOUS位数:14
功能数量:1端子数量:16
最高工作温度:125 °C最低工作温度:-55 °C
封装主体材料:PLASTIC/EPOXY封装代码:TSSOP
封装等效代码:TSSOP16,.25封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH包装方法:TAPE AND REEL
峰值回流温度(摄氏度):NOT SPECIFIED电源:2/6 V
传播延迟(tpd):220 ns认证状态:Not Qualified
座面最大高度:1.2 mm子类别:Counters
最大供电电压 (Vsup):6 V最小供电电压 (Vsup):2 V
标称供电电压 (Vsup):4.5 V表面贴装:YES
技术:CMOS温度等级:MILITARY
端子面层:Tin/Lead (Sn/Pb)端子形式:GULL WING
端子节距:0.65 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED触发器类型:NEGATIVE EDGE
宽度:4.4 mm最小 fmax:24 MHz
Base Number Matches:1

M74HC4020TTR 数据手册

 浏览型号M74HC4020TTR的Datasheet PDF文件第2页浏览型号M74HC4020TTR的Datasheet PDF文件第3页浏览型号M74HC4020TTR的Datasheet PDF文件第4页浏览型号M74HC4020TTR的Datasheet PDF文件第5页浏览型号M74HC4020TTR的Datasheet PDF文件第6页浏览型号M74HC4020TTR的Datasheet PDF文件第7页 
M74HC4020  
14 STAGE BINARY COUNTER  
HIGH SPEED :  
= 70 MHz (TYP.) at V = 6V  
f
MAX  
CC  
LOW POWER DISSIPATION:  
=4µA(MAX.) at T =25°C  
I
CC  
A
HIGH NOISE IMMUNITY:  
= V = 28 % V (MIN.)  
V
NIH  
NIL  
CC  
DIP  
SOP  
TSSOP  
SYMMETRICAL OUTPUT IMPEDANCE:  
|I | = I = 4mA (MIN)  
OH  
OL  
BALANCED PROPAGATION DELAYS:  
t
t
ORDER CODES  
PACKAGE  
PLH  
PHL  
WIDE OPERATING VOLTAGE RANGE:  
(OPR) = 2V to 6V  
TUBE  
T & R  
V
CC  
DIP  
SOP  
M74HC4020B1R  
PIN AND FUNCTION COMPATIBLE WITH  
74 SERIES 4020  
M74HC4020M1R M74HC4020RM13TR  
M74HC4020TTR  
TSSOP  
DESCRIPTION  
The M74HC4020 is an high speed CMOS 14  
STAGE BINARY COUNTER fabricated with  
silicon gate C MOS technology.  
For M74HC4020 twelve kind of divided output are  
provided; 1st and 4th stage to 14th stage.  
The maximum division available at last stage is  
2
A clear input is used to reset the counter to the all  
1/16384 x f at clock.  
IN  
low level state.  
A
high level on CLEAR  
All inputs are equipped with protection circuits  
against static discharge and transient excess  
voltage.  
accomplishes the reset function. A negative  
transition on the CLOCK input increments the  
counter by one.  
PIN CONNECTION AND IEC LOGIC SYMBOLS  
July 2001  
1/11  

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