M74HC4024C1

更新时间： 2024-11-06 13:10:11

品牌	Logo	应用领域
意法半导体 - STMICROELECTRONICS		计数器
页数	文件大小	规格书
11页	248K
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中文翻译

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数据手册

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M74HC4024C1 数据手册

M54HC4024

M74HC4024

7 STAGE BINARY COUNTER

HIGH SPEED

t_PD= 13 ns (TYP.) AT V_CC= 5 V

LOW POWER DISSIPATION

I_CC= 4 µA (MAX.) AT T_A= 25° C

HIGH NOISE IMMUNITY

V_NIH= V_NIL= 28 % V_CC(MIN.)

OUTPUT DRIVE CAPABILITY

10 LSTTL LOADS

SYMMETRICAL OUTPUT IMPEDANCE

|I_OH|= I_OL= 4 mA (MIN.)

BALANCED PROPAGATION DELAYS

t_PLH= t_PHL

WIDE OPERATING VOLTAGE RANGE

B1R

(Plastic Package)

F1R

(Ceramic Package)

M1R

(Micro Package)

C1R

(Chip Carrier)

V_CC(OPR) = 2 V TO 6 V

PIN AND FUNCTION COMPATIBLE

WITH 4024B

ORDER CODES :

M54HC4024F1R

M74HC4024B1R

M74HC4024M1R

M74HC4024C1R

PIN CONNECTIONS (top view)

DESCRIPTION

The M54/74HC4024 is a high speed CMOS 7-

STAGE BINARY COUNTER fabricated in silicon

gate C²MOS technology. It has the same high

speed performance of LSTTL combined with true

CMOS low power consumption. The HC4024 is a 7

stage Counter. This devices is incremented on the

falling edge (negative transition) of the input clock,

and all its outputs are reset toa low level by applying

a logical high on their reset input. All inputs are

equipped with protection circuits against static dis-

charge and transient excess voltage.

NC =

No Internal

Connection

October 1992

1/11

12 3 4 5 6 7...11

中文翻译

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