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M74HC4028TTR PDF预览

M74HC4028TTR

更新时间: 2024-11-06 05:10:55
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 解码器驱动器逻辑集成电路光电二极管
页数 文件大小 规格书
9页 284K
描述
BCD TO DECIMAL DECODER

M74HC4028TTR 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:TSSOP包装说明:TSSOP, TSSOP16,.25
针数:16Reach Compliance Code:not_compliant
ECCN代码:EAR99HTS代码:8542.39.00.01
风险等级:5.91Is Samacsys:N
系列:HC/UH输入调节:STANDARD
JESD-30 代码:R-PDSO-G16JESD-609代码:e0
长度:5 mm负载电容(CL):50 pF
逻辑集成电路类型:DECIMAL DECODER/DRIVER最大I(ol):0.004 A
功能数量:1端子数量:16
最高工作温度:125 °C最低工作温度:-55 °C
输出极性:TRUE封装主体材料:PLASTIC/EPOXY
封装代码:TSSOP封装等效代码:TSSOP16,.25
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度(摄氏度):NOT SPECIFIED电源:2/6 V
Prop。Delay @ Nom-Sup:56 ns传播延迟(tpd):280 ns
认证状态:Not Qualified座面最大高度:1.2 mm
子类别:Decoder/Drivers最大供电电压 (Vsup):6 V
最小供电电压 (Vsup):2 V标称供电电压 (Vsup):4.5 V
表面贴装:YES技术:CMOS
温度等级:MILITARY端子面层:Tin/Lead (Sn/Pb)
端子形式:GULL WING端子节距:0.65 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:4.4 mmBase Number Matches:1

M74HC4028TTR 数据手册

 浏览型号M74HC4028TTR的Datasheet PDF文件第2页浏览型号M74HC4028TTR的Datasheet PDF文件第3页浏览型号M74HC4028TTR的Datasheet PDF文件第4页浏览型号M74HC4028TTR的Datasheet PDF文件第5页浏览型号M74HC4028TTR的Datasheet PDF文件第6页浏览型号M74HC4028TTR的Datasheet PDF文件第7页 
M74HC4028  
BCD TO DECIMAL DECODER  
HIGH SPEED:  
= 20ns (TYP.) at V = 6V  
t
PD  
CC  
LOW POWER DISSIPATION:  
= 4µA(MAX.) at T =25°C  
I
CC  
A
HIGH NOISE IMMUNITY:  
= V = 28 % V (MIN.)  
V
NIH  
NIL  
CC  
DIP  
SOP  
TSSOP  
SYMMETRICAL OUTPUT IMPEDANCE:  
|I | = I = 4mA (MIN)  
OH  
OL  
BALANCED PROPAGATION DELAYS:  
t
t
ORDER CODES  
PACKAGE  
PLH  
PHL  
WIDE OPERATING VOLTAGE RANGE:  
(OPR) = 2V to 6V  
TUBE  
T & R  
V
CC  
DIP  
SOP  
M74HC4028B1R  
PIN AND FUNCTION COMPATIBLE WITH  
74 SERIES 4028  
M74HC4028M1R M74HC4028RM13TR  
M74HC4028TTR  
TSSOP  
DESCRIPTION  
The M74HC4028 is an high speed CMOS BCD  
TO DECIMAL DECODER fabricated with silicon  
gate C MOS technology.  
A BCD code applied to the four inputs (A to D)  
provides a high level at the selected one of the  
decimal decoded outputs. An illegal BCD code  
such as eleven to fifteen gives a low level at all  
outputs. The device also can be used as 3 TO 8  
LINE DECODER, when D input is assigned as a  
disable input.  
The device is useful for code conversion, address  
decoding, memory selection, demultiplexing, or  
read out decoding.  
All inputs are equipped with protection circuits  
against static discharge and transient excess  
voltage.  
2
PIN CONNECTION AND IEC LOGIC SYMBOLS  
August 2001  
1/9  

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