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M74HC4040TTR PDF预览

M74HC4040TTR

更新时间: 2024-11-06 04:27:23
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 计数器
页数 文件大小 规格书
11页 356K
描述
12 STAGE BINARY COUNTER

M74HC4040TTR 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:TSSOP
包装说明:TSSOP, TSSOP16,.25针数:16
Reach Compliance Code:compliantHTS代码:8542.39.00.01
Factory Lead Time:16 weeks风险等级:5.3
计数方向:UP系列:HC/UH
JESD-30 代码:R-PDSO-G16JESD-609代码:e4
长度:5 mm负载电容(CL):50 pF
负载/预设输入:NO逻辑集成电路类型:BINARY COUNTER
最大频率@ Nom-Sup:20000000 Hz最大I(ol):0.004 A
工作模式:ASYNCHRONOUS湿度敏感等级:3
位数:12功能数量:1
端子数量:16最高工作温度:125 °C
最低工作温度:-55 °C封装主体材料:PLASTIC/EPOXY
封装代码:TSSOP封装等效代码:TSSOP16,.25
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
包装方法:TAPE AND REEL峰值回流温度(摄氏度):260
电源:2/6 V传播延迟(tpd):220 ns
认证状态:Not Qualified座面最大高度:1.2 mm
子类别:Counters最大供电电压 (Vsup):6 V
最小供电电压 (Vsup):2 V标称供电电压 (Vsup):4.5 V
表面贴装:YES技术:CMOS
温度等级:MILITARY端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式:GULL WING端子节距:0.65 mm
端子位置:DUAL处于峰值回流温度下的最长时间:40
触发器类型:NEGATIVE EDGE宽度:4.4 mm
最小 fmax:24 MHzBase Number Matches:1

M74HC4040TTR 数据手册

 浏览型号M74HC4040TTR的Datasheet PDF文件第2页浏览型号M74HC4040TTR的Datasheet PDF文件第3页浏览型号M74HC4040TTR的Datasheet PDF文件第4页浏览型号M74HC4040TTR的Datasheet PDF文件第5页浏览型号M74HC4040TTR的Datasheet PDF文件第6页浏览型号M74HC4040TTR的Datasheet PDF文件第7页 
M74HC4040  
12 STAGE BINARY COUNTER  
HIGH SPEED :  
= 70 MHz (TYP.) at V = 6V  
f
MAX  
CC  
LOW POWER DISSIPATION:  
=4µA(MAX.) at T =25°C  
I
CC  
A
HIGH NOISE IMMUNITY:  
= V = 28 % V (MIN.)  
V
NIH  
NIL  
CC  
DIP  
SOP  
TSSOP  
SYMMETRICAL OUTPUT IMPEDANCE:  
|I | = I = 4mA (MIN)  
OH  
OL  
BALANCED PROPAGATION DELAYS:  
ORDER CODES  
PACKAGE  
t
t
PLH  
PHL  
TUBE  
T & R  
WIDE OPERATING VOLTAGE RANGE:  
(OPR) = 2V to 6V  
V
DIP  
SOP  
M74HC4040B1R  
CC  
M74HC4040M1R M74HC4040RM13TR  
M74HC4040TTR  
PIN AND FUNCTION COMPATIBLE WITH  
74 SERIES 4040  
TSSOP  
DESCRIPTION  
transition on the CLOCK input increments the  
counter by one.  
For M74HC4040 each division stage has an  
The M74HC4040 is an high speed CMOS 12  
STAGE BINARY COUNTER fabricated with  
2
silicon gate C MOS technology.  
output; the final frequency is 1/4096 f .  
IN  
A clear input is used to reset the counter to the all  
All inputs are equipped with protection circuits  
against static discharge and transient excess  
voltage.  
low level state.  
A
high level on CLEAR  
accomplishes the reset function. A negative  
PIN CONNECTION AND IEC LOGIC SYMBOLS  
July 2001  
1/11  

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