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M74HC4028 PDF预览

M74HC4028

更新时间: 2024-11-08 22:57:55
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 解码器
页数 文件大小 规格书
10页 247K
描述
BCD TO DECIMAL DECODER

M74HC4028 数据手册

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M54HC4028  
M74HC4028  
BCD TO DECIMAL DECODER  
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HIGH SPEED  
tPD = 18 ns (TYP.) AT VCC = 5 V  
LOW POWER DISSIPATION  
ICC = 4 µA (MAX.) AT TA = 25 °C  
HIGH NOISE IMMUNITY  
VNIH = VNIL = 28 % VCC (MIN.)  
OUTPUT DRIVE CAPABILITY  
10 LSTTL LOADS  
SYMMETRICAL OUTPUT IMPEDANCE  
|IOH| = IOL = 4 mA (MIN.)  
BALANCED PROPAGATION DELAYS  
tPLH = tPHL  
WIDE OPERATING VOLTAGE RANGE  
B1R  
(Plastic Package)  
F1R  
(Ceramic Package)  
M1R  
(Micro Package)  
C1R  
(Chip Carrier)  
VCC (OPR) = 2 V TO 6 V  
PIN AND FUNCTION COMPATIBLE  
WITH 4028B  
ORDER CODES :  
M54HC4028F1R  
M74HC4028B1R  
M74HC4028M1R  
M74HC4028C1R  
PIN CONNECTIONS (top view)  
DESCRIPTION  
The M54/74HC4028 is a high speed CMOS BCD-  
TO-DECIMAL DECODER fabricated in silicon gate  
C2MOS technology. It has the same highspeed per-  
formance of LSTTL combined with true CMOS low  
power consumption. A BCD code applied to the four  
inputs (A to D) provides a high level at the selected  
one of the decimal decoded outputs. An illegal BCD  
code such as eleven to fifteen gives a low level at  
all outputs. The device also can be used as 3-TO-  
8-LINE DECODER, when D input is assigned as a  
disable input. The device is useful for code conver-  
sion, address decoding, memory selection, demulti-  
plexing, or read out decoding.  
NC =  
No Internal  
Connection  
All inputs are equipped with protection circuits  
against static discharge and transient excess volt-  
age.  
October 1992  
1/10  

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