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M74HC4022TTR PDF预览

M74HC4022TTR

更新时间: 2024-11-05 20:06:39
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 光电二极管输出元件逻辑集成电路触发器
页数 文件大小 规格书
11页 420K
描述
HC/UH SERIES, SYN POSITIVE EDGE TRIGGERED 8-BIT UP RING COUNTER, PDSO16, TSSOP-16

M74HC4022TTR 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Obsolete零件包装代码:TSSOP
包装说明:TSSOP, TSSOP16,.25针数:16
Reach Compliance Code:not_compliantHTS代码:8542.39.00.01
风险等级:5.78其他特性:JOHNSON COUNTER WITH 8 DECODED OUTPUTS; TCO OUTPUT; GATED CLOCK
计数方向:UP系列:HC/UH
JESD-30 代码:R-PDSO-G16JESD-609代码:e0
长度:5 mm负载电容(CL):50 pF
负载/预设输入:NO逻辑集成电路类型:RING COUNTER
最大频率@ Nom-Sup:21000000 Hz最大I(ol):0.004 A
工作模式:SYNCHRONOUS位数:8
功能数量:1端子数量:16
最高工作温度:125 °C最低工作温度:-55 °C
封装主体材料:PLASTIC/EPOXY封装代码:TSSOP
封装等效代码:TSSOP16,.25封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH峰值回流温度(摄氏度):NOT SPECIFIED
电源:2/6 V传播延迟(tpd):240 ns
认证状态:Not Qualified座面最大高度:1.2 mm
子类别:Counters最大供电电压 (Vsup):6 V
最小供电电压 (Vsup):2 V标称供电电压 (Vsup):4.5 V
表面贴装:YES技术:CMOS
温度等级:MILITARY端子面层:Tin/Lead (Sn/Pb)
端子形式:GULL WING端子节距:0.65 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
触发器类型:POSITIVE EDGE宽度:4.4 mm
最小 fmax:25 MHzBase Number Matches:1

M74HC4022TTR 数据手册

 浏览型号M74HC4022TTR的Datasheet PDF文件第2页浏览型号M74HC4022TTR的Datasheet PDF文件第3页浏览型号M74HC4022TTR的Datasheet PDF文件第4页浏览型号M74HC4022TTR的Datasheet PDF文件第5页浏览型号M74HC4022TTR的Datasheet PDF文件第6页浏览型号M74HC4022TTR的Datasheet PDF文件第7页 
M74HC4022  
OCTAL COUNTER/DIVIDER  
HIGH SPEED :  
= 63 MHz (TYP.) at V = 6V  
f
MAX  
CC  
LOW POWER DISSIPATION:  
=4µA(MAX.) at T =25°C  
I
CC  
A
HIGH NOISE IMMUNITY:  
= V = 28 % V (MIN.)  
V
NIH  
NIL  
CC  
DIP  
SOP  
TSSOP  
SYMMETRICAL OUTPUT IMPEDANCE:  
|I | = I = 4mA (MIN)  
OH  
OL  
BALANCED PROPAGATION DELAYS:  
t
t
ORDER CODES  
PACKAGE  
PLH  
PHL  
WIDE OPERATING VOLTAGE RANGE:  
(OPR) = 2V to 6V  
TUBE  
T & R  
V
CC  
DIP  
SOP  
M74HC4022B1R  
PIN AND FUNCTION COMPATIBLE WITH  
74 SERIES 4022  
M74HC4022M1R M74HC4022RM13TR  
M74HC4022TTR  
TSSOP  
DESCRIPTION  
The M74HC4022 is an high speed CMOS OCTAL  
COUNTER/DIVIDER fabricated with silicon gate  
C MOS technology.  
It contains a 4-stage divide-by-8 Johnson counter  
with 8 decoded outputs (Q0 - Q7) and a Carry-out  
bit. This counter is advanced on the positive edge  
of the clock signal when CE input is held low, or is  
advanced on the negative edge of clock enable  
signal when CLOCK input is held high, and the  
selected one of eight outputs goes high. Holding  
the CLEAR input high clears the counter to zero  
regardless of the other input conditions.  
All inputs are equipped with protection circuits  
against static discharge and transient excess  
voltage.  
2
PIN CONNECTION AND IEC LOGIC SYMBOLS  
July 2001  
1/11  

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