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M74HC4022C1R PDF预览

M74HC4022C1R

更新时间: 2024-11-22 22:57:55
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 计数器触发器逻辑集成电路输出元件
页数 文件大小 规格书
12页 258K
描述
OCTAL COUNTER/DIVIDER

M74HC4022C1R 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:QFN包装说明:QCCJ, LDCC20,.4SQ
针数:20Reach Compliance Code:compliant
HTS代码:8542.39.00.01风险等级:5.84
Is Samacsys:N其他特性:JOHNSON COUNTER WITH 8 DECODED OUTPUTS; TCO OUTPUT; GATED CLOCK
计数方向:UP系列:HC/UH
JESD-30 代码:S-PQCC-J20JESD-609代码:e3
长度:8.9662 mm负载电容(CL):50 pF
负载/预设输入:NO逻辑集成电路类型:RING COUNTER
最大频率@ Nom-Sup:25000000 Hz最大I(ol):0.004 A
工作模式:SYNCHRONOUS位数:8
功能数量:1端子数量:20
最高工作温度:85 °C最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装代码:QCCJ
封装等效代码:LDCC20,.4SQ封装形状:SQUARE
封装形式:CHIP CARRIER峰值回流温度(摄氏度):NOT SPECIFIED
电源:2/6 V传播延迟(tpd):40 ns
认证状态:Not Qualified座面最大高度:4.57 mm
子类别:Counters最大供电电压 (Vsup):6 V
最小供电电压 (Vsup):2 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:Matte Tin (Sn)
端子形式:J BEND端子节距:1.27 mm
端子位置:QUAD处于峰值回流温度下的最长时间:NOT SPECIFIED
触发器类型:POSITIVE EDGE宽度:8.9662 mm
最小 fmax:25 MHzBase Number Matches:1

M74HC4022C1R 数据手册

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M54HC4022  
M74HC4022  
OCTAL COUNTER/DIVIDER  
.
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.
.
.
.
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HIGH SPEED  
fMAX = 57 MHz (TYP.) at VCC = 5 V  
LOW POWER DISSIPATION  
ICC 4 µA (MAX.) at TA = 25 °C  
HIGH NOISE IMMUNITY  
VNIH = VNIL = 28 % VCC (MIN.)  
OUTPUT DRIVE CAPABILITY  
10 LSTTL LOADS  
SYMMETRICAL OUTPUT IMPEDANCE  
|IOH| = IOL = 4 mA (MIN.)  
BALANCED PROPAGATION DELAYS  
tPLH = tPHL  
WIDE OPERATING VOLTAGE RANGE  
B1R  
(Plastic Package)  
F1R  
(Ceramic Package)  
M1R  
(Micro Package)  
C1R  
(Chip Carrier)  
VCC (OPR) = 2 V to 6 V  
PIN AND FUNCTION COMPATIBLE  
WITH 4022B  
ORDER CODES :  
M54HC4022F1R  
M74HC4022B1R  
M74HC4022M1R  
M74HC4022C1R  
PIN CONNECTIONS (top view)  
DESCRIPTION  
The M54/74HC4022 isa high speed CMOSOCTAL  
COUNTER/DIVIDER fabricated in silicon gate  
C2MOS technology.  
It has the same high speed performance of LSTTL  
combined with true CMOS low power consumption.  
It contains a 4-stage divide-by-8 Johnson counter  
with 8 decoded outputs (Q0-Q7) and a Carry-out bit.  
This counter is advanced on the positive edge of the  
clock signal when CLOCK ENABLE input is held  
low, or is advanced on the negative edge of clock  
enable signal when CLOCK input is held high, and  
the selected one of eight outputs goes high.Holding  
the CLEAR input high clears the counter to zero re-  
gardless of the other input conditions. All inputs are  
equipped with protection circuits against static dis-  
charge and transient excess voltage.  
NC =  
No Internal  
Connection  
October 1992  
1/12  

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