M74HC4017C1

更新时间： 2024-11-23 13:10:11

品牌	Logo	应用领域
意法半导体 - STMICROELECTRONICS		计数器触发器逻辑集成电路输出元件
页数	文件大小	规格书
12页	260K
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中文翻译

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数据手册

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M74HC4017C1 数据手册

M54HC4017

M74HC4017

DECADE COUNTER/DIVIDER

HIGH SPEED

t_PD= 21 ns (typ.) AT V_CC= 5V

LOW POWER DISSIPATION

I_CC= 4 µA (MAX.) AT T_A= 25 ^oC

HIGH NOISE IMMUNITY

V_NIH= V_NIL= 28 % V_CC(MIN.)

OUTPUT DRIVE CAPABILITY

10 LSTTL LOADS

SYMMETRICAL OUTPUT IMPEDANCE

|I_OH| = I_OL= 4 mA (MIN.)

BALANCED PROPAGATION DELAYS

t_PLH= t_PHL

WIDE OPERATING VOLTAGE RANGE

B1R

(Plastic Package)

F1R

(Ceramic Package)

M1R

(Micro Package)

C1R

(Chip Carrier)

V_CC(OPR) = 2 V TO 6 V

PIN AND FUNCTION COMPATIBLEWITH

4017B

ORDER CODES :

M54HC4017F1R

M74HC4017B1R

M74HC4017M1R

M74HC4017C1R

PIN CONNECTIONS (top view)

DESCRIPTION

The M54/74HC4017 is a high speed CMOS DE-

CADE COUNTER/DIVIDER fabricated in silicon

gate C2MOS technology. It has the same high

speed performance of LSTTL combined with true

CMOS low power consumption.

The M54/74HC4017 is a 5-stage Johnson counter

with 10 decoded outputs. Each of the decoded out-

puts is normally low and sequentially goes high on

the low to high transition ofthe clock input.Each out-

put stays high for one clock period of the 10 clock

period cycle. The CARRY output goes low to high

after OUTPUT 10 goes low, and can be used in con-

junction with the CLOCK ENABLE to cascade sev-

eral stages.

The CLOCK ENABLE input disables counting when

in the high state. A RESET input is also provided

which when taken high sets all the decoded outputs

low.

NC =

No Internal

Connection

October 1992

1/12

12 3 4 5 6 7...12

中文翻译

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与M74HC4017C1相关器件

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M74HC4020	STMICROELECTRONICS	获取价格	HC4020 14 STAGE BINARY COUNTER HC4040 12 STAGE BINARY COUNTER
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