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M74HC165M1R PDF预览

M74HC165M1R

更新时间: 2024-10-31 22:19:43
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 移位寄存器
页数 文件大小 规格书
12页 478K
描述
8 BIT PISO SHIFT REGISTER

M74HC165M1R 数据手册

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M74HC165  
8 BIT PISO SHIFT REGISTER  
HIGH SPEED :  
= 15ns (TYP.) at V = 6V  
t
PD  
CC  
LOW POWER DISSIPATION:  
=4µA(MAX.) at T =25°C  
I
CC  
A
HIGH NOISE IMMUNITY:  
= V = 28 % V (MIN.)  
V
NIH  
NIL  
CC  
DIP  
SOP  
TSSOP  
T & R  
SYMMETRICAL OUTPUT IMPEDANCE:  
|I | = I = 4mA (MIN)  
OH  
OL  
BALANCED PROPAGATION DELAYS:  
t
t
ORDER CODES  
PACKAGE  
PLH  
PHL  
WIDE OPERATING VOLTAGE RANGE:  
(OPR) = 2V to 6V  
TUBE  
V
CC  
DIP  
SOP  
M74HC165B1R  
M74HC165M1R  
PIN AND FUNCTION COMPATIBLE WITH  
74 SERIES 165  
M74HC165RM13TR  
M74HC165TTR  
TSSOP  
DESCRIPTION  
The M74HC165 is an high speed CMOS 8 BIT  
PISO SHIFT REGISTER fabricated with silicon  
gate C MOS technology.  
This device contains eight clocked master slave  
RS flip-flops connected as a shift register, with  
be high. The two clock input perform identically;  
one can be used as a clock inhibit by applying a  
high signal; to permit this operation clocking is  
accomplished through a 2 input nor gate.  
To avoid double clocking, however, the inhibit  
signal should only go high while the clock is high.  
Otherwise the rising inhibit signal will cause the  
same response as rising clock edge.  
2
auxiliary  
gating  
to  
provide  
over-riding  
asynchronous parallel entry. Parallel data enters  
when the shift/load input is low. The parallel data  
can change while shift/load is low, provided that  
the recommended set-up and hold times are  
observed. For clocked operation, shift/load must  
All inputs are equipped with protection circuits  
against static discharge and transient excess  
voltage.  
PIN CONNECTION AND IEC LOGIC SYMBOLS  
July 2001  
1/12  

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