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M54HCT393F1R PDF预览

M54HCT393F1R

更新时间: 2024-11-01 22:25:27
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 计数器触发器逻辑集成电路
页数 文件大小 规格书
12页 257K
描述
DUAL BINARY COUNTER

M54HCT393F1R 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Obsolete零件包装代码:DIP
包装说明:DIP, DIP14,.3针数:14
Reach Compliance Code:not_compliantHTS代码:8542.39.00.01
风险等级:5.35计数方向:UP
系列:HCTJESD-30 代码:R-GDIP-T14
JESD-609代码:e0负载电容(CL):50 pF
负载/预设输入:NO逻辑集成电路类型:BINARY COUNTER
最大频率@ Nom-Sup:28000000 Hz最大I(ol):0.004 A
工作模式:ASYNCHRONOUS位数:4
功能数量:2端子数量:14
最高工作温度:125 °C最低工作温度:-55 °C
封装主体材料:CERAMIC, GLASS-SEALED封装代码:DIP
封装等效代码:DIP14,.3封装形状:RECTANGULAR
封装形式:IN-LINE峰值回流温度(摄氏度):NOT SPECIFIED
电源:5 V传播延迟(tpd):77 ns
认证状态:Not Qualified座面最大高度:5.08 mm
子类别:Counters最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:NO技术:CMOS
温度等级:MILITARY端子面层:Tin/Lead (Sn/Pb)
端子形式:THROUGH-HOLE端子节距:2.54 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
触发器类型:NEGATIVE EDGE宽度:7.62 mm
Base Number Matches:1

M54HCT393F1R 数据手册

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M54HCT393  
M74HCT393  
DUAL BINARY COUNTER  
.
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HIGH SPEED  
fMAX = 80 MHz (TYP.) AT VCC = 5 V  
LOW POWER DISSIPATION  
ICC = 4 µA (MAX.) AT TA = 25 °C  
COMPATIBLE WITH TTL OUTPUTS  
VIH = 2V (MIN.) VIL = 0.8V (MAX)  
OUTPUT DRIVE CAPABILITY  
10 LSTTL LOADS  
SYMMETRICAL OUTPUT IMPEDANCE  
|IOH| = IOL = 4 mA (MIN.)  
BALANCED PROPAGATION DELAYS  
tPLH = tPHL  
PIN AND FUNCTION COMPATIBLE  
B1R  
(Plastic Package)  
F1R  
(Ceramic Package)  
M1R  
(Micro Package)  
C1R  
(Chip Carrier)  
WITH 54/74LS393  
ORDER CODES :  
M54HCT393F1R  
M74HCT393M1R  
M74HCT393B1R  
M74HCT393C1R  
DESCRIPTION  
PIN CONNECTIONS (top view)  
The M54/74HCT393 is a high speed CMOS DUAL  
BINARY COUNTER fabricated in silicon gate  
C2MOS technology. It has the same high speed  
performance of LSTTL combined with true COMS  
low power consumption.  
This counter circuit contains independent ripple  
carry counters and two 4-bit ripple carry binary  
counters, which can be cascated to create a single  
divide by 256 counter.  
Each 4-bit counter is incremented on the high to low  
transition (negative edge) of the clock input,and  
each has an independent clear input. When clear is  
set to high all four bits of each counter are set to a  
low level. This enables count truncation and allows  
the implementation of divide by  
N counter  
configurations.  
This integrated circuit has input and output  
characteristics that are fully compatible with 54/74  
LSTTL logic families. M54/74HCT devices are  
designed to directly interface HSC2MOS systems  
with TTL and NMOS components. They are also  
plug in replacements for LSTTL devices giving a  
reduction of power consumption.  
NC =  
No Internal  
Connection  
All inputs are equipped with protection circuits  
against static discharge and transient excess  
voltage.  
October 1993  
1/12  

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