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M54HCT643F1R PDF预览

M54HCT643F1R

更新时间： 2024-11-01 22:57:55
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 总线驱动器总线收发器逻辑集成电路输出元件
页数 文件大小 规格书
11页 267K
描述
OCTAL BUS TRANSCEIVER3-STATE: HCT245 NON INVERTING HCT640 INVERTING, HCT643 INVERTING/NON INVERTING

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中文翻译

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M54HCT643F1R 技术参数

是否无铅： 含铅是否Rohs认证： 不符合
生命周期：Obsolete零件包装代码：DIP
包装说明：CERAMIC, DIP-20针数：20
Reach Compliance Code：not_compliantHTS代码：8542.39.00.01
风险等级：5.5Is Samacsys：N
其他特性：WITH DIRECTION CONTROL; INVERTED OUTPUTS PORT A TO B控制类型：COMMON CONTROL
计数方向：BIDIRECTIONAL系列：HCT
JESD-30 代码：R-GDIP-T20JESD-609代码：e0
负载电容（CL）：150 pF逻辑集成电路类型：BUS TRANSCEIVER
最大I（ol）：0.006 A位数：8
功能数量：1端口数量：2
端子数量：20最高工作温度：125 °C
最低工作温度：-55 °C输出特性：3-STATE
输出极性：TRUE封装主体材料：CERAMIC, GLASS-SEALED
封装代码：DIP封装等效代码：DIP20,.3
封装形状：RECTANGULAR封装形式：IN-LINE
峰值回流温度（摄氏度）：NOT SPECIFIED电源：5 V
Prop。Delay @ Nom-Sup：33 ns传播延迟（tpd）：45 ns
认证状态：Not Qualified座面最大高度：5.71 mm
子类别：Bus Driver/Transceivers最大供电电压 (Vsup)：5.5 V
最小供电电压 (Vsup)：4.5 V标称供电电压 (Vsup)：5 V
表面贴装：NO技术：CMOS
温度等级：MILITARY端子面层：Tin/Lead (Sn/Pb)
端子形式：THROUGH-HOLE端子节距：2.54 mm
端子位置：DUAL处于峰值回流温度下的最长时间：NOT SPECIFIED
翻译：N/A宽度：7.62 mm
Base Number Matches：1

M54HCT643F1R 数据手册

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M54/74HCT245/640/643  
M54/74HCT245/640/643  
OCTAL BUS TRANSCEIVER (3-STATE): HCT245 NON INVERTING  
HCT640 INVERTING, HCT643 INVERTING/NON INVERTING  
.
HIGH SPEED  
PD = 10 ns (TYP.) at VCC = 5V  
t
.
.
.
.
.
.
LOW POWER DISSIPATION  
ICC = 4 µA (MAX.) at TA = 25 oC  
COMPATIBLE WITH TTL OUTPUTS  
B1R  
(Plastic Package)  
F1R  
V
IH = 2V (MIN.) VIL = 0.8V (MAX.)  
(Ceramic Package)  
OUTPUT DRIVE CAPABILITY  
15 LSTTL LOADS  
SYMMETRICAL OUTPUT IMPEDANCE  
|IOH| = IOL = 6 mA (MIN)  
BALANCED PROPAGATION DELAYS  
tPLH = tPHL  
PIN AND FUNCTION COMPATIBLE  
WITH 54/74LS245/640/643  
M1R  
C1R  
(Micro Package)  
(Chip Carrier)  
ORDER CODES :  
M54HCTXXXF1R  
M74HCTXXXM1R  
M74HCTXXXB1R  
M74HCTXXXC1R  
DESCRIPTION  
The M54/74HCT245, HCT640 and HCT643 utilise  
silicon gate C2MOS technology to achive operating  
speeds eqivalent to LSTTL devices.  
characteristics that are fully compatible with 54/74  
LSTTL logic families. M54/74HCT devices are  
designed to directly interface HSC2MOS systems  
with TTL and NMOS components. They are also  
plug in replacements for LSTTL devices giving a  
reduction of power consumption.  
IT IS PROHIBITED TO APPLY A SIGNAL TO A  
BUS TERMINAL WHEN IT IS IN OUTPUT MODE  
AND WHEN A BUS THERMINAL IS FLOATING  
(HIGH IMPEDANCE STATE), IT IS REQUESTED  
TO FIX THE INPUT LEVEL BY MEANS OF  
EXTERNAL PULL DOWN OR PULL UP  
RESISTOR.  
Along with the low power dissipation and high noise  
immunity of standad CMOS integrated circuit, it  
possesses the capability to drive 15 LSTTL loads.  
These IC’s are intended for two-way asynchronous  
communication between data buses, and the  
direction of data trasmission is determined by DIR  
input. The enable input (G) can be used to disable  
the device so that the buses are effectively isolated.  
All input are equipped with protection circuits  
against static discharge and transient discharge.  
These integrated circuits have input and output  
PIN CONNECTION (top view)  
HCT245  
HCT640  
HCT643  
October 1993  
1/11  
1234567...11

中文翻译

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