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M54HCT564 PDF预览

M54HCT564

更新时间: 2024-11-01 22:57:55
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 触发器输出元件
页数 文件大小 规格书
13页 270K
描述
OCTAL D-TYPE FLIP FLOP WITH 3 STATE OUTPUT HCT564 INVERTING - HCT574 NON INVERTING

M54HCT564 数据手册

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M54/74HCT564  
M54/74HCT574  
OCTAL D-TYPE FLIP FLOP WITH 3 STATE OUTPUT  
HCT564 INVERTING - HCT574 NON INVERTING  
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HIGH SPEED  
MAX = 62 MHz (TYP.) AT VCC = 5 V  
LOW POWER DISSIPATION  
ICC = 4 µA (MAX.) AT TA = 25 °C  
COMPATIBLE WITH TTL OUTPUTS  
f
V
IH = 2V (MIN.) VIL = 0.8V (MAX)  
B1R  
(Plastic Package)  
F1R  
OUTPUT DRIVE CAPABILITY  
15 LSTTL LOADS  
SYMMETRICAL OUTPUT IMPEDANCE  
IOL = IOH = 6 mA (MIN.)  
BALANCED PROPAGATION DELAYS  
tPLH = tPHL  
(Ceramic Package)  
M1R  
(Micro Package)  
C1R  
(Chip Carrier)  
PIN AND FUNCTION COMPATIBLE  
WITH 54/74LS564/574  
ORDER CODES :  
M54HCTXXXF1R  
M74HCTXXXB1R  
M74HCTXXXM1R  
M74HCTXXXC1R  
DESCRIPTION  
The M54/74HCT564 and M54HCT574 are high  
speed CMOS OCTAL D-TYPE FLIP FLOP WITH 3-  
STATE OUTPUTS fabricated in silicon gate C2MOS  
technology. They have the same high speed per-  
formance of LSTTL combined with true CMOS low  
power comsuption. These 8-bit D-type flip-flops are  
controlled by a clockinput(CK) and anouputenable  
input (OE). On thepositive transition of theclock, the  
Q outputs willbesetto thelogic statethatweresetup  
at the D inputs (HCT574) or their complements  
(HCT564).  
ternal operation of flip-flops. That is, theold data can  
be retained or the new data can be entered even  
while the outputs are off. The application engineer  
has a choice of combination of inverting and non-in-  
verting outputs. The 3-state output configuration  
and the wide choice of outline make bus-organized  
systemssimple. Allinputs are equipped withprotec-  
tion circuits against static discharge and transient  
excess voltage. This integrated circuit has input and  
output characteristics that are fully compatible with  
54/74 LSTTL logic families. M54/74HCT devices  
are designed to directly interface HSC2MOS sys-  
tems with TTL and NMOS components. They are  
also plug in replacements for LSTTL devices giving  
a reduction of power consumption.  
While the OE input is low, the eight outputs will be  
in a normal logic state (high or low logic level), and  
while high level, the outputs will be in a high imped-  
ance state. The output control does not affect the in-  
PIN CONNECTION (top view)  
HCT564  
HCT574  
HCT564  
HCT574  
September 1993  
1/13  

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