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M54HCT563F1R PDF预览

M54HCT563F1R

更新时间: 2024-11-01 23:13:51
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 总线驱动器总线收发器逻辑集成电路输出元件
页数 文件大小 规格书
13页 271K
描述
OCTAL D-TYPE LATCH WITH 3 STATE OUTPUT HCT563 INVERTING - HCT573 NON INVERTING

M54HCT563F1R 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Obsolete零件包装代码:DIP
包装说明:DIP, DIP20,.3针数:20
Reach Compliance Code:not_compliantHTS代码:8542.39.00.01
风险等级:5.92其他特性:BROADSIDE VERSION OF 533
系列:HCTJESD-30 代码:R-GDIP-T20
JESD-609代码:e0负载电容(CL):150 pF
逻辑集成电路类型:BUS DRIVER最大I(ol):0.006 A
位数:8功能数量:1
端口数量:2端子数量:20
最高工作温度:125 °C最低工作温度:-55 °C
输出特性:3-STATE输出极性:INVERTED
封装主体材料:CERAMIC, GLASS-SEALED封装代码:DIP
封装等效代码:DIP20,.3封装形状:RECTANGULAR
封装形式:IN-LINE峰值回流温度(摄氏度):NOT SPECIFIED
电源:5 VProp。Delay @ Nom-Sup:45 ns
传播延迟(tpd):59 ns认证状态:Not Qualified
座面最大高度:5.71 mm子类别:FF/Latches
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:NO
技术:CMOS温度等级:MILITARY
端子面层:Tin/Lead (Sn/Pb)端子形式:THROUGH-HOLE
端子节距:2.54 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:7.62 mm
Base Number Matches:1

M54HCT563F1R 数据手册

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M54/74HCT563  
M54/74HCT573  
OCTAL D-TYPE LATCH WITH 3 STATE OUTPUT  
HCT563 INVERTING - HCT573 NON INVERTING  
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HIGH SPEED  
PD = 18 ns (TYP.) AT VCC = 5 V  
LOW POWER DISSIPATION  
ICC = 4 µA (MAX.) AT TA = 25 °C  
COMPATIBLE WITH TTL OUTPUTS  
t
V
IH = 2V (MIN.) VIL = 0.8V (MAX.)  
B1R  
(Plastic Package)  
F1R  
OUTPUT DRIVE CAPABILITY  
15 LSTTL LOADS  
SYMMETRICAL OUTPUT IMPEDANCE  
IOL = IOH = 6 mA (MIN.)  
BALANCED PROPAGATION DELAYS  
tPLH = tPHL  
(Ceramic Package)  
M1R  
(Micro Package)  
C1R  
(Chip Carrier)  
PIN AND FUNCTION COMPATIBLE  
WITH 54/74LS563/573  
ORDER CODES :  
M54HCTXXXF1R  
M74HCTXXXB1R  
M74HCTXXXM1R  
M74HCTXXXC1R  
DESCRIPTION  
The M54/74HCT563 and M54HCT573 are high  
speed CMOS OCTAL LATCH WITH 3-STATE  
OUTPUTS fabricated with silicon gate C2MOS  
technology.  
These ICs achive the high speed operation similar  
to equivalent LSTTL while maintaining the CMOS  
low power dissipation.  
These 8 bit D-Type latches are controlled by a latch  
enable input (LE) and a output enable input (OE).  
While the LE input is held at a high level, the Q  
outputs will follow the data input precisely or  
inversely. When the LE is taken low, the Q outputs  
will be latched precisely or inversely at the logic level  
of D input data. While the OE input is at low level,  
the eight outputs will be in a normal logic state (high  
or low logic level) and while high level the outpts will  
be in a high impedance state.  
The application designer has  
a choise of  
combination of inverting and non inverting outputs.  
This integrated circuit has input and output  
characteristics that are fully compatible with 54/74  
LSTTL logic families. M54/74HCT devices are  
designed to directly interface HSC2MOS systems  
with TTL and NMOS components. They are also  
plug in replacements for LSTTL devices giving a  
reduction of power consumption.  
All inputs are equipped with protection circuits  
against discharge and transient excess voltage.  
PIN CONNECTION (top view)  
HCT563  
HCT573  
HCT563  
HCT573  
October 1993  
1/13  

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OCTAL BUS TRANSCEIVER3-STATE: HCT245 NON INVERTING HCT640 INVERTING, HCT643 INVERTING/NON
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