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M54HC131 PDF预览

M54HC131

更新时间: 2024-11-20 22:46:39
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS /
页数 文件大小 规格书
12页 264K
描述
3 TO 8 LINE DECODER/LATCH

M54HC131 数据手册

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M54HC131  
M74HC131  
3 TO 8 LINE DECODER/LATCH  
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HIGH SPEED  
tPD = 22 ns (TYP.) AT VCC = 5 V  
LOW POWER DISSIPATION  
ICC = 4 µA (MAX.) at TA = 25 °C  
HIGH NOISE IMMUNITY  
VNIH = VNIL = 28 % VCC (MIN.)  
OUTPUT DRIVE CAPABILITY  
10 LSTTL LOADS  
SYMMETRICAL OUTPUT IMPEDANCE  
| IOH | = IOL = 4 mA (MIN.)  
BALANCED PROPAGATION DELAYS  
tPLH = tPHL  
B1R  
(Plastic Package)  
F1R  
(Ceramic Package)  
WIDE OPERATING VOLTAGE RANGE  
VCC(OPR) = 2 V to 6 V  
PIN AND FUNCTION COMPATIBLE WITH  
54/74LS131  
M1R  
(Micro Package)  
C1R  
(Chip Carrier)  
ORDER CODES :  
M54HC131F1R  
M74HC131B1R  
M74HC131M1R  
M74HC131C1R  
PIN CONNECTIONS (top view)  
DESCRIPTION  
The M54/74HC131 is a high speed CMOS 3 TO 8  
LINE DECODER/LATCH fabricated in silicon gate  
C2MOS technology.  
It has the same high speed performance of LSTTL  
combined with true CMOS low power consumption.  
This device is a DECODER/LATCH capable of se-  
lectingarbitrarily one of eight outputs by three binary  
inputs A, B, and C, in this case, the selected output  
is at logic ”low”.  
Also, when ENABLE input G1 is set low or ENABLE  
input G2 is set high, selection is inhibited regardless  
of other input signals and all the outputs are at high.  
All inputs are equipped with protection circuits  
against static discharge and transient excess volt-  
age.  
NC =  
No Internal  
Connection  
October 1992  
1/12  

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