Datasheet > 逻辑 > 栅极> M54HC132DG

M54HC132DG

更新时间： 2024-06-20 14:40:53

品牌	Logo	应用领域
意法半导体 - STMICROELECTRONICS		/
页数	文件大小	规格书
9页	235K
描述
抗辐照四路2输入施密特与非门

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中文翻译

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技术参数
数据手册

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M54HC132DG 技术参数

生命周期：	Active	Reach Compliance Code：	compliant
风险等级：	5.83	逻辑集成电路类型：	NAND GATE

M54HC132DG 数据手册

M54HC10

M74HC10

TRIPLE 3-INPUT NAND GATE

HIGH SPEED

t_PD= 6 ns (TYP.) AT V_CC= 5 V

LOW POWER DISSIPATION

I_CC= 1 µA (MAX.) AT T_A= 25 °C

HIGH NOISE IMMUNITY

V_NIH= V_NIL= 28 % V_CC(MIN.)

OUTPUT DRIVE CAPABILITY

10 LSTTL LOADS

SYMMETRICAL OUTPUT IMPEDANCE

IOH = I_OL= 4 mA (MIN.)

BALANCED PROPAGATION DELAYS

t_PLH= t_PHL

WIDE OPERATING VOLTAGE RANGE

B1R

(Plastic Package)

F1R

(Ceramic Package)

M1R

(Micro Package)

C1R

(Chip Carrier)

V_CC(OPR) = 2 V TO 6 V

PIN AND FUNCTION COMPATIBLE WITH

54/74LS10

ORDER CODES :

M54HC10F1R

M74HC10B1R

M74HC10M1R

M74HC10C1R

PIN CONNECTIONS (top view)

DESCRIPTION

The M54/74HC10 is a high speed CMOS TRIPLE

3-INPUT NAND GATE fabricated with silicon gate

C²MOS technology.

It has the same high speed performance of LSTTL

combined with true CMOS low power consumption.

The internal circuit is composed of 3 stages includ-

ing buffer output, which enables high noise im-

munity and stable output.

All inputs are equipped with protection circuits

against static discharge and transient excess volt-

age.

INPUT AND OUTPUT EQUIVALENT CIRCUIT

NC =

No Internal

Connection

December 1992

1/9

12 3 4 5 6 7...9

中文翻译

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