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M54HC137_04 PDF预览

M54HC137_04

更新时间: 2024-11-04 05:00:59
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS /
页数 文件大小 规格书
10页 227K
描述
RAD-HARD 3 TO 8 LINE DECODER/LATCH (INVERTING)

M54HC137_04 数据手册

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M54HC137  
RAD-HARD 3 TO 8 LINE DECODER/LATCH (INVERTING)  
HIGH SPEED:  
=18ns (TYP.) at V = 6V  
t
PD  
CC  
LOW POWER DISSIPATION:  
= 2µA (MAX.) at T =25°C  
I
CC  
A
HIGH NOISE IMMUNITY:  
= V = 28% V (MIN.)  
V
NIH  
NIL  
CC  
DILC-16  
FPC-16  
SYMMETRICAL OUTPUT IMPEDANCE:  
|I | = I = 4mA (MIN)  
OH  
OL  
BALANCED PROPAGATION DELAYS:  
t
t
ORDER CODES  
PACKAGE  
PLH  
PHL  
WIDE OPERATING VOLTAGE RANGE:  
(OPR) = 2V to 6V  
FM  
EM  
V
CC  
DILC  
FPC  
M54HC137D  
M54HC137K  
M54HC137D1  
M54HC137K1  
PIN AND FUNCTION COMPATIBLE WITH  
54 SERIES 137  
SPACE GRADE-1: ESA SCC QUALIFIED  
50 krad QUALIFIED, 100 krad AVAILABLE ON  
REQUEST  
NO SEL UNDER HIGH LET HEAVY IONS  
IRRADIATION  
to high, the addresses present at the select inputs  
(A, B, and C) is stored in the latches. As long as  
GL remains high no address changes will be  
recognized. Output enable pins G1 and G2,  
control the state of the outputs independently of  
the select or latch-enable inputs. All the outputs  
are high unless G1 is high and G2 is low. The  
54HC137 is ideally suited for the implementation  
of glitch-free decoders in stored-address  
application in bus oriented systems.  
DEVICE FULLY COMPLIANT WITH  
SCC-9205-013  
DESCRIPTION  
The M54HC137 is an high speed CMOS 3 TO 8  
LINE DECODER/LATCH (INVERTING) fabricated  
with silicon gate C MOS technology.  
This device is a 3 to 8 line decoder with latches on  
the three address inputs. When GL goes from low  
2
All inputs are equipped with protection circuits  
against static discharge and transient excess  
voltage.  
PIN CONNECTION  
March 2004  
1/10  

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