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M54HC139 PDF预览

M54HC139

更新时间: 2024-11-03 22:46:39
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS /
页数 文件大小 规格书
9页 241K
描述
M54HC138F1R M74HC138M1R M74HC138B1R M74HC138C1R

M54HC139 数据手册

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M54HC139  
M74HC139  
DUAL 2 TO 4 DECODER/DEMULTIPLEXER  
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HIGH SPEED  
tPD = 12 ns (TYP.) AT VCC = 5 V  
LOW POWER DISSIPATION  
ICC = 4 µA (MAX.) AT TA = 25 °C  
HIGH NOISE IMMUNITY  
VNIH = VNIL = 28 % VCC (MIN.)  
OUTPUT DRIVE CAPABILITY  
10 LSTTL LOADS  
SYMMETRICAL OUTPUT IMPEDANCE  
|IOH| = IOL = 4 mA (MIN.)  
BALANCED PROPAGATION DELAYS  
tPLH = tPHL  
WIDE OPERATING VOLTAGE RANGE  
B1R  
(Plastic Package)  
F1R  
(Ceramic Package)  
M1R  
(Micro Package)  
C1R  
(Chip Carrier)  
VCC (OPR) = 2 V TO 6 V  
PIN AND FUNCTION COMPATIBLE  
WITH 54/74LS139  
ORDER CODES :  
M54HC139F1R  
M74HC139B1R  
M74HC139M1R  
M74HC139C1R  
DESCRIPTION  
PIN CONNECTIONS (top view)  
The M54/74HC139 is a high speed CMOS DUAL  
TWO LINE TO FOUR LINE DECODER/DEMULTI-  
PLEXER fabricated in silicon gate C2MOS technol-  
ogy. It has the same high speed performance of  
LSTTL combined with true CMOS low power con-  
sumption. The active low enable input can be used  
for gating or as a data input for demultiplexing ap-  
plications. While the enable input is held high, all  
four outputs are high independently of the other in-  
puts. All inputs are equipped with protection circuits  
against static discharge and transient excess volt-  
age.  
INPUT AND OUTPUT EQUIVALENT CIRCUIT  
NC =  
No Internal  
Connection  
February 1993  
1/9  

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