M54HC148KG

更新时间： 2024-11-04 13:02:07

品牌	Logo	应用领域
意法半导体 - STMICROELECTRONICS		编码器
页数	文件大小	规格书
11页	254K
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中文翻译

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数据手册

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M54HC148KG 数据手册

M54HC148

M74HC148

8 TO 3 LINE PRIORITY ENCODER

HIGH SPEED

t_PD= 15 ns (TYP.) AT V_CC= 5 V

LOW POWER DISSIPATION

I_CC= 4 µA (MAX.) AT T_A= 25 °C

HIGH NOISE IMMUNITY

V_NIH= V_NIL= 28 % V_CC(MIN.)

OUTPUT DRIVE CAPABILITY

10 LSTTL LOADS

SYMMETRICAL OUTPUT IMPEDANCE

I_OH= I_OL= 4 mA (MIN.)

BALANCED PROPAGATION DELAYS

t_PLH= t_PHL

WIDE OPERATING VOLTAGE RANGE

B1R

(Plastic Package)

F1R

(Ceramic Package)

M1R

(Micro Package)

C1R

(Chip Carrier)

V_CC(OPR) = 2 V TO 6 V

PIN AND FUNCTION COMPATIBLE

WITH 54/74LS148

ORDER CODES :

M54HC148F1R

M74HC148B1R

M74HC148M1R

M74HC148C1R

DESCRIPTION

The M54/74HC148 is a high speed CMOS 8-TO-3

LINE PRIORITY ENCODER fabricated in silicon

gate C²MOS technology.

PIN CONNECTIONS (top view)

It has the same high speed performance for LSTTL

combined with true CMOS low power consumption.

The M54/74HC148 encodes eight data lines to

three-line (4-2-1) binary (octal). Cascading circuitry

(enable input EI and enable output EO) has been

provided to allow octal expansion without the need

for external circuitry. Data inputs are active at the

low logic level.

All inputs are equipped with protection circuits

against static discharge and transient excess volt-

age.

INPUT AND OUTPUT EQUIVALENT CIRCUIT

NC =

No Internal

Connection

October 1992

1/11

12 3 4 5 6 7...11

中文翻译

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