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M54HC148F1R PDF预览

M54HC148F1R

更新时间: 2024-11-03 22:46:39
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 运算电路逻辑集成电路输出元件编码器
页数 文件大小 规格书
11页 254K
描述
8 TO 3 LINE PRIORITY ENCODER

M54HC148F1R 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:DIP包装说明:CERAMIC, DIP-16
针数:16Reach Compliance Code:not_compliant
HTS代码:8542.39.00.01风险等级:5.78
Is Samacsys:N其他特性:8 TO 3 LINE PRIORITY ENCODER; CASCADABLE; WITH GROUP SELECT OUTPUT
系列:HC/UHJESD-30 代码:R-GDIP-T16
JESD-609代码:e0负载电容(CL):50 pF
逻辑集成电路类型:ENCODER位数:8
功能数量:1端子数量:16
最高工作温度:125 °C最低工作温度:-55 °C
封装主体材料:CERAMIC, GLASS-SEALED封装代码:DIP
封装等效代码:DIP16,.3封装形状:RECTANGULAR
封装形式:IN-LINE电源:2/6 V
传播延迟(tpd):45 ns认证状态:Not Qualified
座面最大高度:5.08 mm子类别:Arithmetic Circuits
最大供电电压 (Vsup):6 V最小供电电压 (Vsup):2 V
标称供电电压 (Vsup):5 V表面贴装:NO
技术:CMOS温度等级:MILITARY
端子面层:Tin/Lead (Sn/Pb)端子形式:THROUGH-HOLE
端子节距:2.54 mm端子位置:DUAL
宽度:7.62 mmBase Number Matches:1

M54HC148F1R 数据手册

 浏览型号M54HC148F1R的Datasheet PDF文件第2页浏览型号M54HC148F1R的Datasheet PDF文件第3页浏览型号M54HC148F1R的Datasheet PDF文件第4页浏览型号M54HC148F1R的Datasheet PDF文件第5页浏览型号M54HC148F1R的Datasheet PDF文件第6页浏览型号M54HC148F1R的Datasheet PDF文件第7页 
M54HC148  
M74HC148  
8 TO 3 LINE PRIORITY ENCODER  
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.
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HIGH SPEED  
tPD = 15 ns (TYP.) AT VCC = 5 V  
LOW POWER DISSIPATION  
ICC = 4 µA (MAX.) AT TA = 25 °C  
HIGH NOISE IMMUNITY  
VNIH = VNIL = 28 % VCC (MIN.)  
OUTPUT DRIVE CAPABILITY  
10 LSTTL LOADS  
SYMMETRICAL OUTPUT IMPEDANCE  
IOH = IOL = 4 mA (MIN.)  
BALANCED PROPAGATION DELAYS  
tPLH = tPHL  
WIDE OPERATING VOLTAGE RANGE  
B1R  
(Plastic Package)  
F1R  
(Ceramic Package)  
M1R  
(Micro Package)  
C1R  
(Chip Carrier)  
VCC (OPR) = 2 V TO 6 V  
PIN AND FUNCTION COMPATIBLE  
WITH 54/74LS148  
ORDER CODES :  
M54HC148F1R  
M74HC148B1R  
M74HC148M1R  
M74HC148C1R  
DESCRIPTION  
The M54/74HC148 is a high speed CMOS 8-TO-3  
LINE PRIORITY ENCODER fabricated in silicon  
gate C2MOS technology.  
PIN CONNECTIONS (top view)  
It has the same high speed performance for LSTTL  
combined with true CMOS low power consumption.  
The M54/74HC148 encodes eight data lines to  
three-line (4-2-1) binary (octal). Cascading circuitry  
(enable input EI and enable output EO) has been  
provided to allow octal expansion without the need  
for external circuitry. Data inputs are active at the  
low logic level.  
All inputs are equipped with protection circuits  
against static discharge and transient excess volt-  
age.  
INPUT AND OUTPUT EQUIVALENT CIRCUIT  
NC =  
No Internal  
Connection  
October 1992  
1/11  

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