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M54HC138D1 PDF预览

M54HC138D1

更新时间: 2024-11-04 05:00:59
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 解码器驱动器逻辑集成电路
页数 文件大小 规格书
9页 176K
描述
RAD-HARD 3 TO 8 LINE DECODER (INVERTING)

M54HC138D1 技术参数

是否Rohs认证:不符合生命周期:Obsolete
零件包装代码:DIP包装说明:CERAMIC, DIP-16
针数:16Reach Compliance Code:not_compliant
ECCN代码:EAR99HTS代码:8542.39.00.01
风险等级:5.17Is Samacsys:N
系列:HCT输入调节:STANDARD
JESD-30 代码:R-CDIP-T16JESD-609代码:e0
长度:20.32 mm负载电容(CL):50 pF
逻辑集成电路类型:OTHER DECODER/DRIVER最大I(ol):0.004 A
功能数量:1端子数量:16
最高工作温度:125 °C最低工作温度:-55 °C
输出极性:INVERTED封装主体材料:CERAMIC, METAL-SEALED COFIRED
封装代码:DIP封装等效代码:DIP16,.3
封装形状:RECTANGULAR封装形式:IN-LINE
峰值回流温度(摄氏度):NOT SPECIFIED电源:2/6 V
最大电源电流(ICC):0.08 mAProp。Delay @ Nom-Sup:38 ns
传播延迟(tpd):45 ns认证状态:Not Qualified
座面最大高度:3.83 mm子类别:Decoder/Drivers
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:NO
技术:CMOS温度等级:MILITARY
端子面层:Tin/Lead (Sn/Pb)端子形式:THROUGH-HOLE
端子节距:2.54 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED总剂量:50k Rad(Si) V
宽度:7.62 mmBase Number Matches:1

M54HC138D1 数据手册

 浏览型号M54HC138D1的Datasheet PDF文件第2页浏览型号M54HC138D1的Datasheet PDF文件第3页浏览型号M54HC138D1的Datasheet PDF文件第4页浏览型号M54HC138D1的Datasheet PDF文件第5页浏览型号M54HC138D1的Datasheet PDF文件第6页浏览型号M54HC138D1的Datasheet PDF文件第7页 
M54HC138  
RAD-HARD 3 TO 8 LINE DECODER (INVERTING)  
HIGH SPEED:  
= 13ns (TYP.) at V  
t
= 6V  
CC  
PD  
LOW POWER DISSIPATION:  
= 4µA(MAX.) at T =25°C  
I
CC  
A
HIGH NOISE IMMUNITY:  
= V = 28% V (MIN.)  
V
NIH  
NIL  
CC  
DILC-16  
FPC-16  
SYMMETRICAL OUTPUT IMPEDANCE:  
|I | = I = 4mA (MIN)  
OH  
OL  
BALANCED PROPAGATION DELAYS:  
t
t
ORDER CODES  
PACKAGE  
PLH  
PHL  
WIDE OPERATING VOLTAGE RANGE:  
(OPR) = 2V to 6V  
FM  
EM  
V
CC  
DILC  
FPC  
M54HC138D  
M54HC138K  
M54HC138D1  
M54HC138K1  
PIN AND FUNCTION COMPATIBLE WITH  
54 SERIES 138  
SPACE GRADE-1: ESA SCC QUALIFIED  
50 krad QUALIFIED, 100 krad AVAILABLE ON  
REQUEST  
NO SEL UNDER HIGH LET HEAVY IONS  
IRRADIATION  
If the device is enabled, 3 binary select inputs (A,  
B, and C) determine which one of the outputs will  
go low. If enable input G1 is held low or either G2A  
or G2B is held high, the decoding function is  
inhibited and all the 8 outputs go high. Three  
enable inputs are provided to ease cascade  
connection and application of address decoders  
for memory systems.  
DEVICE FULLY COMPLIANT WITH  
SCC-9408-046  
DESCRIPTION  
The M54HC138 is an high speed CMOS 3 TO 8  
LINE DECODER fabricated with silicon gate  
All inputs are equipped with protection circuits  
against static discharge and transient excess  
voltage.  
2
C MOS technology.  
PIN CONNECTION  
March 2004  
1/9  

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