M36W0R6050T1

更新时间： 2024-11-19 04:18:51

品牌	Logo	应用领域
意法半导体 - STMICROELECTRONICS		闪存静态存储器
页数	文件大小	规格书
22页	221K
描述
64 Mbit (4 Mb 】16, Multiple Bank, Burst) Flash memory and 32 Mbit (2 Mb 】16) PSRAM, multi-chip package

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中文翻译

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数据手册

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M36W0R6050T1 数据手册

M36W0R6050T1

M36W0R6050B1

64 Mbit (4 Mb ×16, Multiple Bank, Burst) Flash memory

and 32 Mbit (2 Mb ×16) PSRAM, multi-chip package

Features

■ Multi-Chip Package

– 1 die of 64 Mbit (4 Mb × 16) Flash memory

– 1 die of 32 Mbit (2 Mb × 16) Pseudo SRAM

FBGA

■ Supply voltage

– V

= V

= 1.7 V to 1.95 V

DDQF

DDF

DDP

Stacked TFBGA88

(ZA)

■ Low power consumption

■ Electronic signature

– Manufacturer Code: 20h

– Device code (top flash configuration),

M36W0R6050T1: 8810h

■ Block locking

– Device code (bottom flash configuration),

M36W0R6050B1: 8811h

– All blocks locked at Power-up

– Any combination of blocks can be locked

■ Package

– WP for Block Lock-Down

– ECOPACK®

■ Security

– 128-bit user programmable OTP cells

– 64-bit unique device number

Flash memory

■ Programming time

■ Common Flash Interface (CFI)

– 8 µs by Word typical for Fast Factory

Program

■ 100 000 program/erase cycles per block

– Double/Quadruple Word Program option

– Enhanced Factory Program options

PSRAM

■ Access time: 70 ns

■ Memory blocks

■ Asynchronous Page Read

– Page size: 8 words

– Multiple Bank memory array: 4 Mbit Banks

– Parameter Blocks (Top or Bottom location)

– First access within page: 70 ns

– Subsequent read within page: 20 ns

■ Synchronous / Asynchronous Read

– Synchronous Burst Read mode: 66 MHz

■ Three Power-down modes

– Deep Power-Down

– Asynchronous/ Synchronous Page Read

mode

– Random Access: 70 ns

– Partial Array Refresh of 4 Mbits

– Partial Array Refresh of 8 Mbits

■ Dual operations

– Program Erase in one Bank while Read in

others

– No delay between Read and Write

operations

January 2007

1/22

www.st.com

12 3 4 5 6 7...22

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