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M36W0T7050T0ZAQF PDF预览

M36W0T7050T0ZAQF

更新时间: 2024-11-23 18:50:11
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 静态存储器内存集成电路
页数 文件大小 规格书
18页 443K
描述
SPECIALTY MEMORY CIRCUIT, PBGA88, 8 X 10 MM, 0.80 MM PITCH, LEAD FREE, TFBGA-88

M36W0T7050T0ZAQF 技术参数

是否Rohs认证: 符合生命周期:Transferred
零件包装代码:BGA包装说明:8 X 10 MM, 0.80 MM PITCH, LEAD FREE, TFBGA-88
针数:88Reach Compliance Code:unknown
HTS代码:8542.32.00.71风险等级:5.15
最长访问时间:70 ns其他特性:PSRAM IS ORGANIZED AS 2M X 16
JESD-30 代码:R-PBGA-B88JESD-609代码:e1
长度:10 mm内存密度:134217728 bit
内存集成电路类型:MEMORY CIRCUIT内存宽度:16
混合内存类型:FLASH+PSRAM功能数量:1
端子数量:88字数:8388608 words
字数代码:8000000工作模式:ASYNCHRONOUS
最高工作温度:85 °C最低工作温度:-30 °C
组织:8MX16封装主体材料:PLASTIC/EPOXY
封装代码:TFBGA封装等效代码:BGA88,8X12,32
封装形状:RECTANGULAR封装形式:GRID ARRAY, THIN PROFILE, FINE PITCH
峰值回流温度(摄氏度):260电源:1.8,3/3.3 V
认证状态:Not Qualified座面最大高度:1.2 mm
子类别:Other Memory ICs最大供电电压 (Vsup):2 V
最小供电电压 (Vsup):1.7 V表面贴装:YES
技术:CMOS温度等级:OTHER
端子面层:TIN SILVER COPPER端子形式:BALL
端子节距:0.8 mm端子位置:BOTTOM
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:8 mm
Base Number Matches:1

M36W0T7050T0ZAQF 数据手册

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M36W0T7050T0  
M36W0T7050B0  
128Mbit (Multiple Bank, 8Mb x 16, Burst) Flash Memory  
32Mbit (2M x16) PSRAM, Dual Supply, Multi-Chip Package  
FEATURES SUMMARY  
MULTI-CHIP PACKAGE  
Figure 1. Package  
1 die of 128 Mbit (8Mb x16, Multiple Bank,  
Burst) Flash Memory  
1 die of 32 Mbit (2Mb x16) Pseudo SRAM  
SUPPLY VOLTAGE  
VDDF = 1.7 to 2V  
VDDP = VDDQ = 2.7 to 3.3V  
FBGA  
VPP = 12V for fast Program (optional)  
ELECTRONIC SIGNATURE  
Manufacturer Code: 20h  
Device Code (Top Flash Configuration)  
M36W0T7050T0: 881Eh  
TFBGA88 (ZA)  
x 10mm  
Device Code (Bottom Flash  
Configuration) M36W0T7050B0: 881Fh  
PACKAGE  
Compliant with Lead-Free Soldering  
Processes  
SECURITY  
Lead-Free Versions  
128 bit user programmable OTP cells  
64 bit unique device number  
FLASH MEMORY  
SYNCHRONOUS / ASYNCHRONOUS READ  
BLOCK LOCKING  
Synchronous Burst Read mode: 40MHz  
Asynchronous/ Synchronous Page Read  
mode  
All blocks locked at power-up  
Any combination of blocks can be locked  
WPF for Block Lock-Down  
Random Access: 70ns  
SYNCHRONOUS BURST READ SUSPEND  
PROGRAMMINTIME  
COMMON FLASH INTERFACE (CFI)  
100,000 PROGRAM/ERASE CYCLES per  
BLOCK  
8µs by Word typical for Fast Factory  
Program  
PSRAM  
Doble/Quadruple Word Program option  
nhanced Factory Program options  
ACCESS TIME: 70ns  
LOW STANDBY CURRENT: 100µA  
DEEP POWER DOWN CURRENT: 10µA  
BYTE CONTROL: UBP/LBP  
PROGRAMMABLE PARTIAL ARRAY  
8 WORD PAGE ACCESS CAPABILITY: 18ns  
POWER-DOWN MODES  
MEMORY BLOCKS  
Multiple Bank Memory Array: 4 Mbit  
Banks  
Parameter Blocks (Top or Bottom  
location)  
DUAL OPERATIONS  
– Deep Power-Down  
program/erase in one Bank while read in  
others  
No delay between read and write  
operations  
– 4 Mbit Partial Array Refresh  
– 8 Mbit Partial Array Refresh  
– 16 Mbit Partial Array Refresh  
December 2004  
1/18  

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