Datasheet > LMK04803BISQE/NOPB

LMK04803BISQE/NOPB

更新时间： 2024-11-25 11:14:11

品牌	Logo	应用领域
德州仪器 - TI		时钟
页数	文件大小	规格书
140页	2185K
描述
具有双级联 PLL 和集成式 1.9GHz VCO 的低噪声时钟抖动消除器 \| NKD \| 64 \| -40 to 85

阅读下载

中文翻译

获取价格

数据手册
替代型号

如果您发现信息不准确，欢迎纠错

LMK04803BISQE/NOPB 数据手册

浏览型号LMK04803BISQE/NOPB的Datasheet PDF文件第2页

浏览型号LMK04803BISQE/NOPB的Datasheet PDF文件第3页

浏览型号LMK04803BISQE/NOPB的Datasheet PDF文件第4页

浏览型号LMK04803BISQE/NOPB的Datasheet PDF文件第5页

浏览型号LMK04803BISQE/NOPB的Datasheet PDF文件第6页

浏览型号LMK04803BISQE/NOPB的Datasheet PDF文件第7页

Sample &

Buy

Support &

Community

Product

Folder

Tools &

Software

Technical

Documents

LMK04803, LMK04805, LMK04806, LMK04808

SNAS489K –MARCH 2011–REVISED DECEMBER 2014

LMK0480x Low-Noise Clock Jitter Cleaner with Dual Loop PLLs

1 Features

3 Description

The LMK0480x family is the industry's highest

performance clock conditioner with superior clock

jitter cleaning, generation, and distribution with

advanced features to meet next generation system

•

Ultra-Low RMS Jitter Performance

–

111 fs RMS Jitter (12 kHz to 20 MHz)

123 fs RMS Jitter (100 Hz to 20 MHz)

requirements.

The

dual

loop

PLLatinum™

•

Dual Loop PLLatinum™ PLL Architecture

PLL1

architecture is capable of 111 fs rms jitter (12 kHz to

20 MHz) using a low noise VCXO module or sub-200

fs rms jitter (12 kHz to 20 MHz) using a low cost

external crystal and varactor diode.

–

Integrated Low-Noise Crystal Oscillator Circuit

Holdover Mode when Input Clocks are Lost

Automatic or Manual Triggering/Recovery

The dual loop architecture consists of two high-

performance phase-locked loops (PLL), a low-noise

crystal oscillator circuit, and a high-performance

voltage controlled oscillator (VCO). The first PLL

(PLL1) provides low-noise jitter cleaner functionality

while the second PLL (PLL2) performs the clock

generation. PLL1 can be configured to either work

with an external VCXO module or the integrated

crystal oscillator with an external tunable crystal and

varactor diode. When paired with a very narrow loop

bandwidth, PLL1 uses the superior close-in phase

noise (offsets below 50 kHz) of the VCXO module or

the tunable crystal to clean the input clock. The

output of PLL1 is used as the clean input reference to

PLL2 where it locks the integrated VCO. The loop

bandwidth of PLL2 can be optimized to clean the far-

out phase noise (offsets above 50 kHz) where the

integrated VCO outperforms the VCXO module or

tunable crystal used in PLL1.

•

PLL2

–

Normalized PLL Noise Floor of –227 dBc/Hz

Phase Detector Rate up to 155 MHz

OSCin Frequency-Doubler

Integrated Low-Noise VCO

•

2 Redundant Input Clocks with LOS

Automatic and Manual Switch-Over Modes

–

•

50 % Duty Cycle Output Divides, 1 to 1045 (Even

and Odd)

12 LVPECL, LVDS, or LVCMOS Programmable

Outputs

•

Digital Delay: Fixed or Dynamically Adjustable

25 ps Step Analog Delay Control.

14 Differential Outputs. Up to 26 Single Ended.

–

Up to 6 VCXO/Crystal Buffered Outputs

Device Information

•

Clock Rates of up to 1536 MHz

0-Delay Mode

REFERENCE

INPUTS

PART NUMBER

VCO FREQUENCY

Three Default Clock Outputs at Power Up

LMK04803

LMK04805

LMK04806

LMK04808

1840 to 2030 MHz

2148 to 2370 MHz

2370 to 2600 MHz

2750 to 3072 MHz

Multi-Mode: Dual PLL, Single PLL, and Clock

Distribution

•

Industrial Temperature Range: –40 to 85°C

3.15-V to 3.45-V Operation

(1) For all available packages, see the orderable addendum at

the end of the datasheet.

2 Dedicated Buffered/Divided OSCin Clocks

Package: 64-Pin WQFN (9.0 × 9.0 × 0.8 mm)

Simplified Schematic

OSCout0/

OSCout1

0XOWLSOHꢀ³FOHDQ´ꢀ

clocks at different

frequencies

Applications

Crystal or

VCXO

LMX2541

PLL+VCO

Recovered

³GLUW\´ꢀFORFNꢀRUꢀ

clean clock

•

Data Converter Clocking

CLKin0

CLKout0, 1

Backup

Reference

Clock

Wireless Infrastructure

CLKout2

CLKout3

LMK0480x

FPGA

Serializer/

Deserializer

CLKin1

Precision Clock

Conditioner

Networking, SONET/SDH, DSLAM

Medical / Video / Military / Aerospace

Test and Measurement

CLKout4, 5, 6, 7

CLKout8A

CLKout11

CLKout9

DAC

ADC

CPLD

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

12 3 4 5 6 7...140

中文翻译

下载PDF

LMK04803BISQE/NOPB 替代型号

型号	品牌	替代类型	描述	数据表
LMK04803BISQ/NOPB	TI	完全替代	具有双级联 PLL 和集成式 1.9GHz VCO 的低噪声时钟抖动消除器 \| NKD \|
LMK04803BISQX/NOPB	TI	类似代替	具有双级联 PLL 和集成式 1.9GHz VCO 的低噪声时钟抖动消除器 \| NKD \|

与LMK04803BISQE/NOPB相关器件

型号	品牌	获取价格	描述	数据表
LMK04803BISQX/NOPB	TI	获取价格	具有双级联 PLL 和集成式 1.9GHz VCO 的低噪声时钟抖动消除器 \| NKD \|
LMK04805	TI	获取价格	具有双级联 PLL 和集成式 2.2GHz VCO 的低噪声时钟抖动消除器
LMK04805B	TI	获取价格	Low-Noise Clock Jitter Cleaner with Dual Loop PLLs
LMK04805BISQ	TI	获取价格	Low-Noise Clock Jitter Cleaner with Dual Loop PLLs
LMK04805BISQ/NOPB	TI	获取价格	具有双级联 PLL 和集成式 2.2GHz VCO 的低噪声时钟抖动消除器 \| NKD \|
LMK04805BISQE/NOPB	TI	获取价格	Low Noise Clock Jitter Cleaner With Dual Cascaded PLLs and Integrated 2.2 GHz VCO 64-WQFN
LMK04805BISQX/NOPB	TI	获取价格	具有双级联 PLL 和集成式 2.2GHz VCO 的低噪声时钟抖动消除器 \| NKD \|
LMK04806	TI	获取价格	具有双级联 PLL 和集成式 2.5GHz VCO 的低噪声时钟抖动消除器
LMK04806B	TI	获取价格	Low-Noise Clock Jitter Cleaner with Dual Loop PLLs
LMK04806BISQ	TI	获取价格	Low-Noise Clock Jitter Cleaner with Dual Loop PLLs

与LMK04803BISQE/NOPB相关文章

解析光耦仿真器：升级光耦合器技术的必要性
2024-11-18

38
英伟达新一代Blackwell GPU过热问题致交付延迟
2024-11-18

30
国产厂商思特威CMOS图像传感器芯片单月出货超1亿颗，技术创新引领行业发展
2024-11-14

58
台积电5nm和3nm产能利用率达100%，半导体行业景气度持续攀升
2024-11-14

54

产品中心

服务支持

精选活动

关于我们

帮助中心

LMK04803BISQE/NOPB

LMK04803BISQE/NOPB 数据手册

LMK04803BISQE/NOPB 替代型号

与LMK04803BISQE/NOPB相关器件

与LMK04803BISQE/NOPB相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

LMK04803BISQE/NOPB

LMK04803BISQE/NOPB 数据手册

LMK04803BISQE/NOPB 替代型号

与LMK04803BISQE/NOPB相关器件

与LMK04803BISQE/NOPB相关文章

您还可以找

您在本页遇到什么问题？