Datasheet > LMK04821

LMK04821

更新时间： 2024-11-19 11:12:15

品牌	Logo	应用领域
德州仪器 - TI		/
页数	文件大小	规格书
128页	4539K
描述
支持 JESD204B 的超低抖动合成器和抖动消除器

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LMK04821, LMK04826, LMK04828

SNAS605AS –MARCH 2013–REVISED MAY 2020

LMK0482x Ultra Low-Noise JESD204B Compliant

Clock Jitter Cleaner With Dual Loop PLLs

1 Features

2 Applications

•

JEDEC JESD204B Support

Ultra-Low RMS Jitter

•

Wireless Infrastructure

Data Converter Clocking

Networking, SONET/SDH, DSLAM

Medical / Video / Military / Aerospace

Test and Measurement

–

88 fs RMS Jitter (12 kHz to 20 MHz)

91 fs RMS Jitter (100 Hz to 20 MHz)

–162.5 dBc/Hz Noise Floor at 245.76 MHz

•

Up to 14 Differential Device Clocks from PLL2

3 Description

The LMK0482x family is the industry's highest

–

Up to 7 SYSREF Clocks

Maximum Clock Output Frequency 3.1 GHz

performance

clock

conditioner

with

JEDEC

LVPECL, LVDS, HSDS, LCPECL

Programmable Outputs from PLL2

JESD204B support.

The 14 clock outputs from PLL2 can be configured to

drive seven JESD204B converters or other logic

devices, using device and SYSREF clocks. SYSREF

can be provided using both DC and AC coupling. Not

limited to JESD204B applications, each of the 14

outputs can be individually configured as high-

performance outputs for traditional clocking systems.

•

Up to 1 Buffered VCXO/Crystal Output from PLL1

LVPECL, LVDS, 2xLVCMOS Programmable

–

•

Dual Loop PLLatinum™ PLL Architecture

PLL1

–

Up to 3 Redundant Input Clocks

–

Automatic and Manual Switch-Over Modes

Hitless Switching and LOS

The high performance, combined with features such

as the ability to trade off between power or

performance, dual VCOs, dynamic digital delay,

holdover, and glitchless analog delay, make the

LMK0482x family ideal for providing flexible high-

performance clocking trees.

–

Integrated Low-Noise Crystal Oscillator Circuit

Holdover Mode When Input Clocks are Lost

•

PLL2

–

Normalized [1 Hz] PLL Noise Floor of

–227 dBc/Hz

Device Information⁽¹⁾

PART

NUMBER

VCO0

FREQUENCY

VCO1 FREQUENCY

–

Phase Detector Rate up to 155 MHz

OSCin Frequency-Doubler

Two Integrated Low-Noise VCOs

2920 to 3080 MHz

LMK04821

1930 to 2075 MHz

VCO1 Div = ÷2 to ÷8

(÷2 = 1460 to 1540 MHz)

50% Duty Cycle Output Divides, 1 to 32

(even and odd)

LMK04826

LMK04828

1840 to 1970 MHz

2370 to 2630 MHz

2440 to 2505 MHz

2920 to 3080 MHz

•

Precision Digital Delay, Dynamically Adjustable

25-ps Step Analog Delay

(1) For all available packages, see the orderable addendum at

the end of the datasheet.

Multi-Mode: Dual PLL, Single PLL, and Clock

Distribution

Simplified Schematic

•

Industrial Temperature Range: –40 to 85°C

Supports 105°C PCB Temperature (Measured at

Thermal Pad)

•

3.15-V to 3.45-V Operation

Package: 64-Pin QFN (9.0 mm × 9.0 mm × 0.8

mm)

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

12 3 4 5 6 7...128

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与LMK04821相关器件

型号	品牌	获取价格	描述	数据表
LMK04821NKDR	TI	获取价格	支持 JESD204B 的超低抖动合成器和抖动消除器 \| NKD \| 64 \| -40 t
LMK04821NKDT	TI	获取价格	支持 JESD204B 的超低抖动合成器和抖动消除器 \| NKD \| 64 \| -40 t
LMK04826	TI	获取价格	具有集成式 1840 至 1970MHz VCO0 且符合 JESD204B 标准的超低噪
LMK04826B	TI	获取价格	LMK0482xB Ultra Low-Noise JESD204B Compliant Clock Jitter Cleaner with Dual Loop PLLs
LMK04826BISQ/NOPB	TI	获取价格	LMK0482xB Ultra Low-Noise JESD204B Compliant Clock Jitter Cleaner with Dual Loop PLLs
LMK04826BISQE/NOPB	TI	获取价格	LMK0482xB Ultra Low-Noise JESD204B Compliant Clock Jitter Cleaner with Dual Loop PLLs
LMK04826BISQX/NOPB	TI	获取价格	LMK0482xB Ultra Low-Noise JESD204B Compliant Clock Jitter Cleaner with Dual Loop PLLs
LMK04828	TI	获取价格	具有集成式 2370 至 2630MHz VCO0 且符合 JESD204B 标准的超低噪
LMK04828B	TI	获取价格	LMK0482xB Ultra Low-Noise JESD204B Compliant Clock Jitter Cleaner with Dual Loop PLLs
LMK04828BISQ	TI	获取价格	IC OTHER CLOCK GENERATOR, Clock Generator

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