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LMK04821, LMK04826, LMK04828
SNAS605AS –MARCH 2013–REVISED MAY 2020
LMK0482x Ultra Low-Noise JESD204B Compliant
Clock Jitter Cleaner With Dual Loop PLLs
1 Features
2 Applications
1
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JEDEC JESD204B Support
Ultra-Low RMS Jitter
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Wireless Infrastructure
Data Converter Clocking
Networking, SONET/SDH, DSLAM
Medical / Video / Military / Aerospace
Test and Measurement
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88 fs RMS Jitter (12 kHz to 20 MHz)
91 fs RMS Jitter (100 Hz to 20 MHz)
–162.5 dBc/Hz Noise Floor at 245.76 MHz
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Up to 14 Differential Device Clocks from PLL2
3 Description
The LMK0482x family is the industry's highest
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Up to 7 SYSREF Clocks
Maximum Clock Output Frequency 3.1 GHz
performance
clock
conditioner
with
JEDEC
LVPECL, LVDS, HSDS, LCPECL
Programmable Outputs from PLL2
JESD204B support.
The 14 clock outputs from PLL2 can be configured to
drive seven JESD204B converters or other logic
devices, using device and SYSREF clocks. SYSREF
can be provided using both DC and AC coupling. Not
limited to JESD204B applications, each of the 14
outputs can be individually configured as high-
performance outputs for traditional clocking systems.
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Up to 1 Buffered VCXO/Crystal Output from PLL1
LVPECL, LVDS, 2xLVCMOS Programmable
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Dual Loop PLLatinum™ PLL Architecture
PLL1
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Up to 3 Redundant Input Clocks
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Automatic and Manual Switch-Over Modes
Hitless Switching and LOS
The high performance, combined with features such
as the ability to trade off between power or
performance, dual VCOs, dynamic digital delay,
holdover, and glitchless analog delay, make the
LMK0482x family ideal for providing flexible high-
performance clocking trees.
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Integrated Low-Noise Crystal Oscillator Circuit
Holdover Mode When Input Clocks are Lost
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PLL2
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Normalized [1 Hz] PLL Noise Floor of
–227 dBc/Hz
Device Information(1)
PART
NUMBER
VCO0
FREQUENCY
VCO1 FREQUENCY
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Phase Detector Rate up to 155 MHz
OSCin Frequency-Doubler
Two Integrated Low-Noise VCOs
2920 to 3080 MHz
LMK04821
1930 to 2075 MHz
VCO1 Div = ÷2 to ÷8
(÷2 = 1460 to 1540 MHz)
50% Duty Cycle Output Divides, 1 to 32
(even and odd)
LMK04826
LMK04828
1840 to 1970 MHz
2370 to 2630 MHz
2440 to 2505 MHz
2920 to 3080 MHz
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Precision Digital Delay, Dynamically Adjustable
25-ps Step Analog Delay
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
Multi-Mode: Dual PLL, Single PLL, and Clock
Distribution
Simplified Schematic
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Industrial Temperature Range: –40 to 85°C
Supports 105°C PCB Temperature (Measured at
Thermal Pad)
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3.15-V to 3.45-V Operation
Package: 64-Pin QFN (9.0 mm × 9.0 mm × 0.8
mm)
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.