Datasheet > LMK04816

LMK04816

更新时间： 2024-11-19 01:09:31

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LMK04816 Three Input Low-Noise Clock Jitter Cleaner with Dual Loop PLLs

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LMK04816 数据手册

LMK04816

www.ti.com

SNAS597B –JULY 2012–REVISED APRIL 2013

LMK04816 Three Input Low-Noise Clock Jitter Cleaner with Dual Loop PLLs

Check for Samples: LMK04816

1 Introduction

1.1 FEATURES

123

• Ultra-Low RMS Jitter Performance

– 100 fs RMS Jitter (12 kHz to 20 MHz)

– 123 fs RMS Jitter (100 Hz to 20 MHz)

• Dual Loop PLLatinum™ PLL Architecture

– PLL1

• 50% Duty Cycle Output Divides, 1 to 1045

(Even and Odd)

• LVPECL, LVDS, or LVCMOS Programmable

Outputs

• Precision Digital Delay, Fixed or Dynamically

Adjustable

• 25 ps Step Analog Delay Control, up to 575 ps.

• 1/2 Clock Distribution Period Step Digital

Delay, up to 522 Steps

• 13 Differential Outputs. Up to 26 single Ended.

– Up to 5 VCXO/Crystal Buffered Outputs

• Clock Rates of up to 2600 MHz

•

Integrated Low-Noise Crystal Oscillator

Circuit

•

Holdover Mode When Input Clocks are

Lost

–

Automatic or Manual

Triggering/Recovery

– PLL2

• 0-Delay Mode

• Three Default Clock Outputs at Power Up

•

Normalized [1 Hz] PLL Noise Floor of -227

dBc/Hz

•

Phase Detector Rate up to 155 MHz

OSCin Frequency-Doubler

Integrated Low-Noise VCO

• Multi-Mode: Dual PLL, Single PLL, and Clock

Distribution

• Industrial Temperature Range: -40 to 85 °C

• 3.15 V to 3.45 V Operation

• 3 Redundant Input Clocks with LOS

• Package: 64-Pin WQFN (9.0 x 9.0 x 0.8 mm)

– Automatic and Manual Switch-Over Modes

1.2 TARGET APPLICATIONS

•

Data Converter Clocking / Wireless Infrastructure

Networking, SONET/SDH, DSLAM

Medical / Video / Military / Aerospace

Test and Measurement

1.3 DESCRIPTION

The LMK04816 family is the industry's highest performance clock conditioner with superior clock jitter

cleaning, generation, and distribution with advanced features to meet next generation system

requirements. The dual loop PLLatinum™ architecture enables 111 fs rms jitter (12 kHz to 20 MHz) using

a low noise VCXO module or sub-200 fs rms jitter (12 kHz to 20 MHz) using a low cost external crystal

and varactor diode.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PLLatinum is a trademark of Texas Instruments.

All other trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date. Products conform to

specifications per the terms of the Texas Instruments standard warranty. Production

processing does not necessarily include testing of all parameters.

12 3 4 5 6 7...123

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与LMK04816相关器件

型号	品牌	获取价格	描述	数据表
LMK04816BISQ	TI	获取价格	LMK04816 Three Input Low-Noise Clock Jitter Cleaner with Dual Loop PLLs
LMK04816BISQ/NOPB	TI	获取价格	具有双环 PLL 的三输入低噪声时钟抖动消除器 \| NKD \| 64 \| -40 to 8
LMK04816BISQE	TI	获取价格	LMK04816 Three Input Low-Noise Clock Jitter Cleaner with Dual Loop PLLs
LMK04816BISQE/NOPB	TI	获取价格	具有双环 PLL 的三输入低噪声时钟抖动消除器 \| NKD \| 64
LMK04816BISQX	TI	获取价格	LMK04816 Three Input Low-Noise Clock Jitter Cleaner with Dual Loop PLLs
LMK04816BISQX/NOPB	TI	获取价格	具有双环 PLL 的三输入低噪声时钟抖动消除器 \| NKD \| 64
LMK04821	TI	获取价格	支持 JESD204B 的超低抖动合成器和抖动消除器
LMK04821NKDR	TI	获取价格	支持 JESD204B 的超低抖动合成器和抖动消除器 \| NKD \| 64 \| -40 t
LMK04821NKDT	TI	获取价格	支持 JESD204B 的超低抖动合成器和抖动消除器 \| NKD \| 64 \| -40 t
LMK04826	TI	获取价格	具有集成式 1840 至 1970MHz VCO0 且符合 JESD204B 标准的超低噪

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