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LMK04806BISQE/NOPB

更新时间： 2024-11-19 11:11:07
品牌 Logo 应用领域
德州仪器 - TI 时钟外围集成电路晶体
页数 文件大小 规格书
140页 2185K
描述
具有双级联 PLL 和集成式 2.5GHz VCO 的低噪声时钟抖动消除器 | NKD | 64 | -40 to 85

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中文翻译

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LMK04806BISQE/NOPB 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Active零件包装代码：QFN
包装说明：WQFN-64针数：64
Reach Compliance Code：compliantECCN代码：EAR99
Factory Lead Time：1 week风险等级：0.78
JESD-30 代码：S-PQCC-N64JESD-609代码：e3
长度：9 mm湿度敏感等级：3
端子数量：64最高工作温度：85 °C
最低工作温度：-40 °C最大输出时钟频率：2600 MHz
封装主体材料：PLASTIC/EPOXY封装代码：HVQCCN
封装形状：SQUARE封装形式：CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
峰值回流温度（摄氏度）：260主时钟/晶体标称频率：20.5 MHz
座面最大高度：0.8 mm最大压摆率：590 mA
最大供电电压：3.45 V最小供电电压：3.15 V
标称供电电压：3.3 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子面层：Matte Tin (Sn)端子形式：NO LEAD
端子节距：0.5 mm端子位置：QUAD
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：9 mm
uPs/uCs/外围集成电路类型：CLOCK GENERATOR, OTHERBase Number Matches：1

LMK04806BISQE/NOPB 数据手册

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Sample &  
Buy  
Support &  
Community  
Product  
Folder  
Tools &  
Software  
Technical  
Documents  
LMK04803, LMK04805, LMK04806, LMK04808  
SNAS489K –MARCH 2011–REVISED DECEMBER 2014  
LMK0480x Low-Noise Clock Jitter Cleaner with Dual Loop PLLs  
1 Features  
3 Description  
The LMK0480x family is the industry's highest  
performance clock conditioner with superior clock  
jitter cleaning, generation, and distribution with  
advanced features to meet next generation system  
1
•
Ultra-Low RMS Jitter Performance  
–
–
111 fs RMS Jitter (12 kHz to 20 MHz)  
123 fs RMS Jitter (100 Hz to 20 MHz)  
requirements.  
The  
dual  
loop  
PLLatinum™  
•
•
Dual Loop PLLatinum™ PLL Architecture  
PLL1  
architecture is capable of 111 fs rms jitter (12 kHz to  
20 MHz) using a low noise VCXO module or sub-200  
fs rms jitter (12 kHz to 20 MHz) using a low cost  
external crystal and varactor diode.  
–
–
–
Integrated Low-Noise Crystal Oscillator Circuit  
Holdover Mode when Input Clocks are Lost  
Automatic or Manual Triggering/Recovery  
The dual loop architecture consists of two high-  
performance phase-locked loops (PLL), a low-noise  
crystal oscillator circuit, and a high-performance  
voltage controlled oscillator (VCO). The first PLL  
(PLL1) provides low-noise jitter cleaner functionality  
while the second PLL (PLL2) performs the clock  
generation. PLL1 can be configured to either work  
with an external VCXO module or the integrated  
crystal oscillator with an external tunable crystal and  
varactor diode. When paired with a very narrow loop  
bandwidth, PLL1 uses the superior close-in phase  
noise (offsets below 50 kHz) of the VCXO module or  
the tunable crystal to clean the input clock. The  
output of PLL1 is used as the clean input reference to  
PLL2 where it locks the integrated VCO. The loop  
bandwidth of PLL2 can be optimized to clean the far-  
out phase noise (offsets above 50 kHz) where the  
integrated VCO outperforms the VCXO module or  
tunable crystal used in PLL1.  
•
PLL2  
–
–
–
–
Normalized PLL Noise Floor of –227 dBc/Hz  
Phase Detector Rate up to 155 MHz  
OSCin Frequency-Doubler  
Integrated Low-Noise VCO  
•
2 Redundant Input Clocks with LOS  
Automatic and Manual Switch-Over Modes  
–
•
•
50 % Duty Cycle Output Divides, 1 to 1045 (Even  
and Odd)  
12 LVPECL, LVDS, or LVCMOS Programmable  
Outputs  
•
•
•
Digital Delay: Fixed or Dynamically Adjustable  
25 ps Step Analog Delay Control.  
14 Differential Outputs. Up to 26 Single Ended.  
–
Up to 6 VCXO/Crystal Buffered Outputs  
Device Information  
•
•
•
•
Clock Rates of up to 1536 MHz  
0-Delay Mode  
REFERENCE  
INPUTS  
PART NUMBER  
VCO FREQUENCY  
Three Default Clock Outputs at Power Up  
LMK04803  
LMK04805  
LMK04806  
LMK04808  
1840 to 2030 MHz  
2148 to 2370 MHz  
2370 to 2600 MHz  
2750 to 3072 MHz  
Multi-Mode: Dual PLL, Single PLL, and Clock  
Distribution  
2
•
•
•
•
Industrial Temperature Range: –40 to 85°C  
3.15-V to 3.45-V Operation  
(1) For all available packages, see the orderable addendum at  
the end of the datasheet.  
2 Dedicated Buffered/Divided OSCin Clocks  
Package: 64-Pin WQFN (9.0 × 9.0 × 0.8 mm)  
Simplified Schematic  
OSCout0/  
OSCout1  
0XOWLSOHꢀ³FOHDQ´ꢀ  
clocks at different  
frequencies  
2
Applications  
Crystal or  
VCXO  
LMX2541  
PLL+VCO  
Recovered  
³GLUW\´ꢀFORFNꢀRUꢀ  
clean clock  
•
•
•
•
•
Data Converter Clocking  
CLKin0  
CLKout0, 1  
Backup  
Reference  
Clock  
Wireless Infrastructure  
CLKout2  
CLKout3  
LMK0480x  
FPGA  
Serializer/  
Deserializer  
CLKin1  
I
Precision Clock  
Conditioner  
Networking, SONET/SDH, DSLAM  
Medical / Video / Military / Aerospace  
Test and Measurement  
CLKout4, 5, 6, 7  
CLKout8A  
CLKout11  
CLKout9  
IF  
DAC  
ADC  
CPLD  
Q
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,  
intellectual property matters and other important disclaimers. PRODUCTION DATA.  
 
 
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中文翻译

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LMK04806BISQE/NOPB 替代型号

型号 品牌 替代类型 描述 数据表
LMK04806BISQ/NOPB TI

类似代替

 具有双级联 PLL 和集成式 2.5GHz VCO 的低噪声时钟抖动消除器 | NKD |
LMK04806BISQX/NOPB TI

类似代替

 具有双级联 PLL 和集成式 2.5GHz VCO 的低噪声时钟抖动消除器 | NKD |
LMK04805BISQE/NOPB TI

类似代替

 Low Noise Clock Jitter Cleaner With Dual Cascaded PLLs and Integrated 2.2 GHz VCO 64-WQFN

与LMK04806BISQE/NOPB相关器件

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 		具有双级联 PLL 和集成式 2.5GHz VCO 的低噪声时钟抖动消除器 | NKD |
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 		具有双环路 PLL 和集成式 2.9GHz VCO 的低噪声时钟抖动消除器
LMK04808B TI

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 		Low-Noise Clock Jitter Cleaner with Dual Loop PLLs
LMK04808BISQ TI

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 		Low-Noise Clock Jitter Cleaner with Dual Loop PLLs
LMK04808BISQ/NOPB TI

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 		具有双环路 PLL 和集成式 2.9GHz VCO 的低噪声时钟抖动消除器 | NKD |
LMK04808BISQE/NOPB TI

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 		Low-Noise Clock Jitter Cleaner with Dual Loop PLLs and Integrated 2.9 GHz VCO 64-WQFN -40
LMK04808BISQX/NOPB TI

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 		具有双环路 PLL 和集成式 2.9GHz VCO 的低噪声时钟抖动消除器 | NKD |
LMK04816 TI

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 		LMK04816 Three Input Low-Noise Clock Jitter Cleaner with Dual Loop PLLs
LMK04816BISQ TI

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 		LMK04816 Three Input Low-Noise Clock Jitter Cleaner with Dual Loop PLLs
LMK04816BISQ/NOPB TI

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 		具有双环 PLL 的三输入低噪声时钟抖动消除器 | NKD | 64 | -40 to 8

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