5秒后页面跳转
LMK04805BISQE/NOPB PDF预览

LMK04805BISQE/NOPB

更新时间: 2024-11-21 13:09:23
品牌 Logo 应用领域
德州仪器 - TI 时钟
页数 文件大小 规格书
91页 985K
描述
Low Noise Clock Jitter Cleaner With Dual Cascaded PLLs and Integrated 2.2 GHz VCO 64-WQFN -40 to 85

LMK04805BISQE/NOPB 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:QFN
包装说明:HVQCCN,针数:64
Reach Compliance Code:compliantECCN代码:EAR99
Factory Lead Time:6 weeks风险等级:0.95
JESD-30 代码:S-PQCC-N64JESD-609代码:e3
长度:9 mm湿度敏感等级:3
端子数量:64最高工作温度:85 °C
最低工作温度:-40 °C最大输出时钟频率:2370 MHz
封装主体材料:PLASTIC/EPOXY封装代码:HVQCCN
封装形状:SQUARE封装形式:CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
峰值回流温度(摄氏度):260主时钟/晶体标称频率:20.5 MHz
座面最大高度:0.8 mm最大压摆率:590 mA
最大供电电压:3.45 V最小供电电压:3.15 V
标称供电电压:3.3 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:Matte Tin (Sn)端子形式:NO LEAD
端子节距:0.5 mm端子位置:QUAD
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:9 mm
uPs/uCs/外围集成电路类型:CLOCK GENERATOR, OTHERBase Number Matches:1

LMK04805BISQE/NOPB 数据手册

 浏览型号LMK04805BISQE/NOPB的Datasheet PDF文件第2页浏览型号LMK04805BISQE/NOPB的Datasheet PDF文件第3页浏览型号LMK04805BISQE/NOPB的Datasheet PDF文件第4页浏览型号LMK04805BISQE/NOPB的Datasheet PDF文件第5页浏览型号LMK04805BISQE/NOPB的Datasheet PDF文件第6页浏览型号LMK04805BISQE/NOPB的Datasheet PDF文件第7页 
March 29, 2012  
LMK04800 Family  
Low-Noise Clock Jitter Cleaner with Dual Loop PLLs  
1.0 General Description  
2.0 Features  
The LMK04800 family is the industry's highest performance  
clock conditioner with superior clock jitter cleaning, genera-  
tion, and distribution with advanced features to meet next  
generation system requirements. The dual loop PLLat-  
inumarchitecture enables 111 fs rms jitter (12 kHz to 20  
MHz) using a low noise VCXO module or sub-200 fs rms jitter  
(12 kHz to 20 MHz) using a low cost external crystal and var-  
actor diode.  
Ultra-Low RMS Jitter Performance  
111 fs RMS jitter (12 kHz to 20 MHz)  
123 fs RMS jitter (100 Hz to 20 MHz)  
Dual Loop PLLatinum PLL Architecture  
PLL1  
Integrated Low-Noise Crystal Oscillator Circuit  
Holdover mode when input clocks are lost  
Automatic or manual triggering/recovery  
The dual loop architecture consists of two high-performance  
phase-locked loops (PLL), a low-noise crystal oscillator cir-  
cuit, and a high-performance voltage controlled oscillator  
(VCO). The first PLL (PLL1) provides a low-noise jitter cleaner  
function while the second PLL (PLL2) performs the clock gen-  
eration. PLL1 can be configured to either work with an exter-  
nal VCXO module or the integrated crystal oscillator with an  
external tunable crystal and varactor diode. When used with  
a very narrow loop bandwidth, PLL1 uses the superior close-  
in phase noise (offsets below 50 kHz) of the VCXO module  
or the tunable crystal to clean the input clock. The output of  
PLL1 is used as the clean input reference to PLL2 where it  
locks the integrated VCO. The loop bandwidth of PLL2 can  
be optimized to clean the far-out phase noise (offsets above  
50 kHz) where the integrated VCO outperforms the VCXO  
module or tunable crystal used in PLL1.  
PLL2  
Normalized [1 Hz] PLL noise floor of -227 dBc/Hz  
Phase detector rate up to 155 MHz  
OSCin frequency-doubler  
Integrated Low-Noise VCO  
2 redundant input clocks with LOS  
Automatic and manual switch-over modes  
50% duty cycle output divides, 1 to 1045 (even and odd)  
LVPECL, LVDS, or LVCMOS programmable outputs  
Precision digital delay, fixed or dynamically adjustable  
25 ps step analog delay control.  
14 differential outputs. Up to 26 single ended.  
Up to 6 VCXO/Crystal buffered outputs  
Device  
VCO Frequency  
1840 to 2030 MHz  
2148 to 2370 MHz  
2370 to 2600 MHz  
2750 to 3072 MHz  
Clock rates of up to 1536 MHz  
0-delay mode  
LMK04803B  
LMK04805B  
LMK04806B  
LMK04808B  
Three default clock outputs at power up  
Multi-mode: Dual PLL, single PLL, and clock distribution  
Industrial Temperature Range: -40 to 85 °C  
3.15 V to 3.45 V operation  
Package: 64-pin LLP (9.0 x 9.0 x 0.8 mm)  
3.0 Target Applications  
Data Converter Clocking / Wireless Infrastructure  
Networking, SONET/SDH, DSLAM  
Medical / Video / Military / Aerospace  
Test and Measurement  
30102340  
PLLatinumis a trademark of National Semiconductor Corporation.  
TRI-STATE® is a registered trademark of National Semiconductor Corporation.  
© 2012 Texas Instruments Incorporated  
301023 SNAS489I  
www.ti.com  
 
 

LMK04805BISQE/NOPB 替代型号

型号 品牌 替代类型 描述 数据表
LMK04806BISQ/NOPB TI

完全替代

具有双级联 PLL 和集成式 2.5GHz VCO 的低噪声时钟抖动消除器 | NKD |
LMK04806BISQX/NOPB TI

完全替代

具有双级联 PLL 和集成式 2.5GHz VCO 的低噪声时钟抖动消除器 | NKD |
LMK04805BISQ/NOPB TI

完全替代

具有双级联 PLL 和集成式 2.2GHz VCO 的低噪声时钟抖动消除器 | NKD |

与LMK04805BISQE/NOPB相关器件

型号 品牌 获取价格 描述 数据表
LMK04805BISQX/NOPB TI

获取价格

具有双级联 PLL 和集成式 2.2GHz VCO 的低噪声时钟抖动消除器 | NKD |
LMK04806 TI

获取价格

具有双级联 PLL 和集成式 2.5GHz VCO 的低噪声时钟抖动消除器
LMK04806B TI

获取价格

Low-Noise Clock Jitter Cleaner with Dual Loop PLLs
LMK04806BISQ TI

获取价格

Low-Noise Clock Jitter Cleaner with Dual Loop PLLs
LMK04806BISQ/NOPB TI

获取价格

具有双级联 PLL 和集成式 2.5GHz VCO 的低噪声时钟抖动消除器 | NKD |
LMK04806BISQE/NOPB TI

获取价格

具有双级联 PLL 和集成式 2.5GHz VCO 的低噪声时钟抖动消除器 | NKD |
LMK04806BISQX/NOPB TI

获取价格

具有双级联 PLL 和集成式 2.5GHz VCO 的低噪声时钟抖动消除器 | NKD |
LMK04808 TI

获取价格

具有双环路 PLL 和集成式 2.9GHz VCO 的低噪声时钟抖动消除器
LMK04808B TI

获取价格

Low-Noise Clock Jitter Cleaner with Dual Loop PLLs
LMK04808BISQ TI

获取价格

Low-Noise Clock Jitter Cleaner with Dual Loop PLLs