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K6T1008C2C-P

更新时间: 2024-09-19 22:28:11
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三星 - SAMSUNG /
页数 文件大小 规格书
10页 191K
描述
128K x8 bit Low Power CMOS Static RAM

K6T1008C2C-P 数据手册

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PRELIMINARY  
K6T1008C2C Family  
CMOS SRAM  
Document Title  
128K x8 bit Low Power CMOS Static RAM  
Revision History  
Revision No.  
History  
Draft Date  
Remark  
0.0  
Initial draft  
November 22, 1995  
April 15, 1996  
Design target  
Preliminary  
0.1  
1.0  
2.0  
First revision  
- Seperate read and write at ICC, ICC1  
ICC = ICC1 ® Read : 15mA, Write : 35mA  
Finalized  
September 5, 1996  
November 5, 1997  
Final  
Final  
- Add 70ns speed bin for commercial product and 85ns speed  
bin for industrial.  
Revised  
- Improved operating current  
Add typical value.  
ICC Read : 15mA ® 10mA(Remove write current)  
ICC2 : 90mA ® 60mA  
- Speed bin change  
Remove 45ns from commercial part  
Remove 55ns and 100ns from industrial part.  
The attached data sheets are provided by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications and  
products. SAMSUNG Electronics will answer to your questions about device. If you have any questions, please contact the SAMSUNG branch offices.  
Revision 2.0  
1
November 1997  

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