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JANTXV2N4854U PDF预览

JANTXV2N4854U

更新时间: 2024-11-23 00:00:03
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其他 - ETC 晶体晶体管
页数 文件大小 规格书
15页 116K
描述
TRANSISTOR | BJT | PAIR | COMPLEMENTARY | 40V V(BR)CEO | 600MA I(C) | TO-226(6)

JANTXV2N4854U 数据手册

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The documentation and process conversion  
measures necessary to comply with this  
revision shall be completed by 25 November 2001.  
INCH-POUND  
MIL-PRF-19500/421F  
25 August 2001  
SUPERSEDING  
MIL-PRF-19500/421E  
2 April 1998  
PERFORMANCE SPECIFICATION  
SEMICONDUCTOR DEVICE, DUAL TRANSISTOR, UNITIZED, NPN/PNP,  
COMPLEMENTARY, SILICON TYPES 2N3838, 2N4854, AND 2N4854U  
JAN, JANTX, AND JANTXV  
This specification is approved for use by all Departments  
and Agencies the Department of Defense.  
1. SCOPE  
1.1 Scope. This specification covers the performance requirements for unitized, dual transistors which contain a  
pair of electrically isolated complementary NPN and PNP silicon triode transistors in one package. Three levels of  
product assurance are provided for each device type as specified in MIL-PRF-19500.  
1.2 Polarity designation. Voltages and currents of limits and test conditions shown herein apply to the NPN triode.  
For the PNP triode, the values are the same, but the polarity designations shall be the opposite.  
1.3 Physical dimensions. See figures 1 (6 lead flatpak), 2 (similar to T0-77), and 3 (surface mount).  
1.4 Maximum ratings.  
VCBO  
PT at TA = +25 C  
PT at TC = +25 C (1)  
2N3838 (4) 2N4854 (5)  
2N3838 (2)  
One Total  
2N4854 (3)  
One  
Total  
One  
Total  
One  
Total  
Transistor  
Device  
Transistor  
Device  
Transistor  
Device  
Transistor  
Device  
W
W
W
W
W
W
W
W
V dc  
60  
0.25  
0.35  
0.30  
0.60  
0.7  
1.4  
1.0  
2.0  
Lead to case voltage  
V dc  
VEBO  
VCEO  
V1C-2C  
V dc  
IC  
TJ  
C
TSTG  
C
V dc  
5
V dc  
40  
MA dc  
600  
120  
120  
200  
-55 to +200  
(1) TC rating do not apply to surface mount devices (2N4854U).  
(2) For TA > +25 C, derate linearly 1.43 mW/ C one transistor, 2.00 mW/ C both transistors.  
(3) For TA > +25 C, derate linearly 1.71 mW/ C one transistor, 3.43 mW/ C both transistors.  
(4) For TC > +25 C, derate linearly 4.0 mW/ C one transistor, 8.0 mW/ C both transistors.  
(5) For TC > +25 C, derate linearly 5.71 mW/ C one transistor, 11.43 mW/ C both transistors.  
Beneficial comments (recommendations, additions, deletions) and any pertinent data which may be of use in  
improving this document should be addressed to: Defense Supply Center, Columbus, ATTN: DSCC-VAC,  
P.O. Box 3990, Columbus, OH 43216-5000, by using the Standardization Document Improvement Proposal (DD  
Form 1426) appearing at the end of this document or by letter.  
AMSC N/A  
FSC 5961  
DISTRIBUTION STATEMENT A. Approved for public release; distribution is unlimited.  

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