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IS64WV12816DBLS PDF预览

IS64WV12816DBLS

更新时间: 2024-11-20 05:39:35
品牌 Logo 应用领域
美国芯成 - ISSI /
页数 文件大小 规格书
21页 238K
描述
128K x 16 HIGH SPEED ASYNCHRONOUS CMOS STATIC RAM

IS64WV12816DBLS 数据手册

 浏览型号IS64WV12816DBLS的Datasheet PDF文件第2页浏览型号IS64WV12816DBLS的Datasheet PDF文件第3页浏览型号IS64WV12816DBLS的Datasheet PDF文件第4页浏览型号IS64WV12816DBLS的Datasheet PDF文件第5页浏览型号IS64WV12816DBLS的Datasheet PDF文件第6页浏览型号IS64WV12816DBLS的Datasheet PDF文件第7页 
IS61WV12816DALL/DALS  
IS61WV12816DBLL/DBLS  
IS64WV12816DBLL/DBLS  
128K x 16 HIGH SPEED ASYNCHRONOUS  
CMOS STATIC RAM  
MAY2008  
DESCRIPTION  
FEATURES  
TheISSIIS61WV12816DAxx/DBxxandIS64WV12816DBxx  
are high-speed, 2,097,152-bit static RAMs organized as  
131,072 words by 16 bits. It is fabricated usingISSI's high-  
performance CMOS technology. This highly reliable pro-  
cess coupled with innovative circuit design techniques,  
yields high-performance and low power consumption de-  
vices.  
HIGH SPEED: (IS61/64WV12816DALL/DBLL)  
• High-speed access time: 8, 10, 12, 20 ns  
• Low Active Power: 135 mW (typical)  
• Low Standby Power: 12 μW (typical)  
CMOS standby  
LOW POWER: (IS61/64WV12816DALS/DBLS)  
• High-speed access time: 25, 35 ns  
• Low Active Power: 55 mW (typical)  
When CE is HIGH (deselected), the device assumes a  
standby mode at which the power dissipation can be  
reduced down with CMOS input levels.  
• Low Standby Power: 12 μW (typical)  
CMOS standby  
Easy memory expansion is provided by using Chip Enable  
and Output Enable inputs, CE and OE. The active LOW  
Write Enable (WE) controls both writing and reading of the  
memory. A data byte allows Upper Byte (UB) and Lower  
Byte (LB) access.  
• Single power supply  
— VDD 1.65V to 2.2V (IS61WV12816DAxx)  
— VDD 2.4V to 3.6V (IS61/64WV12816DBxx)  
• Fully static operation: no clock or refresh  
required  
TheIS61WV12816DAxx/DBxxandIS64WV12816DBxxare  
packagedintheJEDECstandard44-pinTSOPTypeII and  
48-pin Mini BGA (6mm x 8mm).  
• Three state outputs  
• Data control for upper and lower bytes  
• Industrial and Automotive temperature support  
• Lead-free available  
FUNCTIONAL BLOCK DIAGRAM  
128K x 16  
MEMORY ARRAY  
A0-A16  
DECODER  
VDD  
GND  
I/O0-I/O7  
Lower Byte  
I/O  
DATA  
COLUMN I/O  
CIRCUIT  
I/O8-I/O15  
Upper Byte  
CE  
OE  
WE  
CONTROL  
CIRCUIT  
UB  
LB  
Copyright © 2006 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time  
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to  
obtain the latest version of this device specification before relying on any published information and before placing orders for products.  
Integrated Silicon Solution, Inc. — www.issi.com  
1
Rev. C  
05/01/08  

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