Datasheet > IS61SF25616-7.5B

IS61SF25616-7.5B

更新时间： 2024-09-16 08:47:03

品牌	Logo	应用领域
美国芯成 - ISSI		静态存储器
页数	文件大小	规格书
14页	147K
描述
Cache SRAM, 256KX16, 7.5ns, CMOS, PBGA119, PLASTIC, BGA-119

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数据手册

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IS61SF25616-7.5B 数据手册

ISSI

IS61SF25616

256K x 16 SYNCHRONOUS

FLOW-THROUGH STATIC RAM

PRELIMINARY

MAY1999

FEATURES

DESCRIPTION

• Internal self-timed write cycle

• Individual Byte Write Control and Global Write

The ISSI IS61SF25616 is a high-speed, low-power

synchronous static RAM designed to provide a burstable,

high-performance, secondary cache for the Pentium™,

680X0™, and PowerPC™ microprocessors. It is organized

as 262,144 words by 16 bits, fabricated with ISSI's advanced

CMOStechnology.Thedeviceintegratesa2-bitburstcounter,

high-speed SRAM core, and high-drive capability outputs into

asinglemonolithiccircuit.Allsynchronousinputspassthrough

registers controlled by a positive-edge-triggered single clock

input.

• Clock controlled, registered address, data and

control

• Pentium™ or linear burst sequence control

using MODE input

• Three chip enables for simple depth expansion

and address pipelining

• Common data inputs and data outputs

Write cycles are internally self-timed and are initiated by the

rising edge of the clock input. Write cycles can be from one to

four bytes wide as controlled by the write control inputs.

• JEDEC 100-pin TQFP and

119-pin PBGA package

Separate byte enables allow individual bytes to be written.

BW1 controls DQa, BW2 controls DQb, conditioned by BWE

being LOW. A LOW on GW input would cause all bytes to be

written.

• Single +3.3V, +10%, –5% power supply

• 3.3V I/O supply

• Power-down snooze mode

Bursts can be initiated with either ADSP (Address Status

Processor) or ADSC (Address Status Cache Controller) input

pins.Subsequentburstaddressescanbegeneratedinternally

bytheIS61SF25616andcontrolledbytheADV(burstaddress

advance) input pin.

The mode pin is used to select the burst sequence order,

Linear burst is achieved when this pin is tied LOW. Interleave

burst is achieved when this pin is tied HIGH or left floating.

FAST ACCESS TIME

Symbol

tKQ

Parameter

7.5

8.5

117

8.5

Units

Clock Access Time

Cycle Time

tKC

100

Frenquency

MHz

Note:

1. Shaded area = ADVANCE INFORMATION DATA.

This document contains PRELIMINARY INFORMATION. ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible

Integrated Silicon Solution, Inc. — 1-800-379-4774

PRELIMINARY SR056-1A

05/24/99

12 3 4 5 6 7...14

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与IS61SF25616-7.5B相关器件

型号	品牌	获取价格	描述	数据表
IS61SF25616-7.5TQ	ISSI	获取价格	Cache SRAM, 256KX16, 7.5ns, CMOS, PQFP100, TQFP-100
IS61SF25616-8.5B	ISSI	获取价格	256K x 16, 256K x 18 SYNCHRONOUS FLOW-THROUGH STATIC RAM
IS61SF25616-8.5TQ	ISSI	获取价格	256K x 16, 256K x 18 SYNCHRONOUS FLOW-THROUGH STATIC RAM
IS61SF25616-8.5TQI	ISSI	获取价格	256K x 16, 256K x 18 SYNCHRONOUS FLOW-THROUGH STATIC RAM
IS61SF25616-8B	ISSI	获取价格	256K x 16, 256K x 18 SYNCHRONOUS FLOW-THROUGH STATIC RAM
IS61SF25616-8TQ	ISSI	获取价格	256K x 16, 256K x 18 SYNCHRONOUS FLOW-THROUGH STATIC RAM
IS61SF25616-8TQI	ISSI	获取价格	Cache SRAM, 256KX16, 8ns, CMOS, PQFP100, TQFP-100
IS61SF25618-10B	ISSI	获取价格	Cache SRAM, 256KX18, 10ns, CMOS, PBGA119, PLASTIC, BGA-119
IS61SF25618-10TQ	ISSI	获取价格	256KX18 CACHE SRAM, 10ns, PQFP100, TQFP-100
IS61SF25618-10TQI	ETC	获取价格	x18 Fast Synchronous SRAM

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