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IS61SF25616-11B PDF预览

IS61SF25616-11B

更新时间: 2024-09-15 19:55:55
品牌 Logo 应用领域
美国芯成 - ISSI 静态存储器内存集成电路
页数 文件大小 规格书
14页 147K
描述
Cache SRAM, 256KX16, 11ns, CMOS, PBGA119, PLASTIC, BGA-119

IS61SF25616-11B 技术参数

生命周期:Obsolete零件包装代码:BGA
包装说明:BGA,针数:119
Reach Compliance Code:unknownECCN代码:3A991.B.2.A
HTS代码:8542.32.00.41风险等级:5.84
最长访问时间:11 nsJESD-30 代码:R-PBGA-B119
长度:22 mm内存密度:4194304 bit
内存集成电路类型:CACHE SRAM内存宽度:16
功能数量:1端子数量:119
字数:262144 words字数代码:256000
工作模式:SYNCHRONOUS最高工作温度:70 °C
最低工作温度:组织:256KX16
封装主体材料:PLASTIC/EPOXY封装代码:BGA
封装形状:RECTANGULAR封装形式:GRID ARRAY
并行/串行:PARALLEL认证状态:Not Qualified
座面最大高度:2.41 mm最大供电电压 (Vsup):3.63 V
最小供电电压 (Vsup):3.14 V标称供电电压 (Vsup):3.3 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子形式:BALL
端子节距:1.27 mm端子位置:BOTTOM
宽度:14 mmBase Number Matches:1

IS61SF25616-11B 数据手册

 浏览型号IS61SF25616-11B的Datasheet PDF文件第2页浏览型号IS61SF25616-11B的Datasheet PDF文件第3页浏览型号IS61SF25616-11B的Datasheet PDF文件第4页浏览型号IS61SF25616-11B的Datasheet PDF文件第5页浏览型号IS61SF25616-11B的Datasheet PDF文件第6页浏览型号IS61SF25616-11B的Datasheet PDF文件第7页 
®
ISSI  
IS61SF25616  
256K x 16 SYNCHRONOUS  
FLOW-THROUGH STATIC RAM  
PRELIMINARY  
MAY1999  
FEATURES  
DESCRIPTION  
• Internal self-timed write cycle  
• Individual Byte Write Control and Global Write  
The ISSI IS61SF25616 is a high-speed, low-power  
synchronous static RAM designed to provide a burstable,  
high-performance, secondary cache for the Pentium™,  
680X0™, and PowerPC™ microprocessors. It is organized  
as 262,144 words by 16 bits, fabricated with ISSI's advanced  
CMOStechnology.Thedeviceintegratesa2-bitburstcounter,  
high-speed SRAM core, and high-drive capability outputs into  
asinglemonolithiccircuit.Allsynchronousinputspassthrough  
registers controlled by a positive-edge-triggered single clock  
input.  
• Clock controlled, registered address, data and  
control  
• Pentium™ or linear burst sequence control  
using MODE input  
• Three chip enables for simple depth expansion  
and address pipelining  
• Common data inputs and data outputs  
Write cycles are internally self-timed and are initiated by the  
rising edge of the clock input. Write cycles can be from one to  
four bytes wide as controlled by the write control inputs.  
• JEDEC 100-pin TQFP and  
119-pin PBGA package  
Separate byte enables allow individual bytes to be written.  
BW1 controls DQa, BW2 controls DQb, conditioned by BWE  
being LOW. A LOW on GW input would cause all bytes to be  
written.  
• Single +3.3V, +10%, –5% power supply  
• 3.3V I/O supply  
• Power-down snooze mode  
Bursts can be initiated with either ADSP (Address Status  
Processor) or ADSC (Address Status Cache Controller) input  
pins.Subsequentburstaddressescanbegeneratedinternally  
bytheIS61SF25616andcontrolledbytheADV(burstaddress  
advance) input pin.  
The mode pin is used to select the burst sequence order,  
Linear burst is achieved when this pin is tied LOW. Interleave  
burst is achieved when this pin is tied HIGH or left floating.  
FAST ACCESS TIME  
Symbol  
tKQ  
Parameter  
7.5  
7.5  
8.5  
117  
8
8
8.5  
8.5  
11  
10  
10  
15  
66  
11  
11  
20  
50  
Units  
ns  
Clock Access Time  
Cycle Time  
tKC  
10  
100  
ns  
Frenquency  
90  
MHz  
Note:  
1. Shaded area = ADVANCE INFORMATION DATA.  
This document contains PRELIMINARY INFORMATION. ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible  
product. We assume no responsibility for any errors which may appear in this publication. © Copyright 1999, Integrated Silicon Solution, Inc.  
Integrated Silicon Solution, Inc. — 1-800-379-4774  
PRELIMINARY SR056-1A  
1
05/24/99  

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