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IS61SF12836-12TQ PDF预览

IS61SF12836-12TQ

更新时间: 2024-09-11 23:59:47
品牌 Logo 应用领域
美国芯成 - ISSI 存储内存集成电路静态存储器
页数 文件大小 规格书
16页 114K
描述
x36 Fast Synchronous SRAM

IS61SF12836-12TQ 技术参数

是否无铅:含铅是否Rohs认证:不符合
生命周期:Obsolete零件包装代码:QFP
包装说明:TQFP-100针数:100
Reach Compliance Code:compliantECCN代码:3A991.B.2.A
HTS代码:8542.32.00.41风险等级:5.88
Is Samacsys:N最长访问时间:12 ns
其他特性:INDIVIDUAL BYTE WRITE CONTROLI/O 类型:COMMON
JESD-30 代码:R-PQFP-G100JESD-609代码:e0
长度:20 mm内存密度:4718592 bit
内存集成电路类型:CACHE SRAM内存宽度:36
功能数量:1端子数量:100
字数:131072 words字数代码:128000
工作模式:SYNCHRONOUS最高工作温度:70 °C
最低工作温度:组织:128KX36
输出特性:3-STATE封装主体材料:PLASTIC/EPOXY
封装代码:LQFP封装等效代码:QFP100,.63X.87
封装形状:RECTANGULAR封装形式:FLATPACK, LOW PROFILE
并行/串行:PARALLEL峰值回流温度(摄氏度):240
电源:3.3 V认证状态:Not Qualified
座面最大高度:1.6 mm最大待机电流:0.01 A
最小待机电流:3.14 V子类别:SRAMs
最大压摆率:0.17 mA最大供电电压 (Vsup):3.63 V
最小供电电压 (Vsup):3.135 V标称供电电压 (Vsup):3.3 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:GULL WING端子节距:0.65 mm
端子位置:QUAD处于峰值回流温度下的最长时间:30
宽度:14 mmBase Number Matches:1

IS61SF12836-12TQ 数据手册

 浏览型号IS61SF12836-12TQ的Datasheet PDF文件第2页浏览型号IS61SF12836-12TQ的Datasheet PDF文件第3页浏览型号IS61SF12836-12TQ的Datasheet PDF文件第4页浏览型号IS61SF12836-12TQ的Datasheet PDF文件第5页浏览型号IS61SF12836-12TQ的Datasheet PDF文件第6页浏览型号IS61SF12836-12TQ的Datasheet PDF文件第7页 
®
IS61SF12832  
IS61SF12836  
128K x 32, 128K x 36 SYNCHRONOUS  
FLOW-THROUGH STATIC RAM  
ISSI  
APRIL 2001  
FEATURES  
DESCRIPTION  
The ISSI IS61SF12832 and IS61SF12836 are high-speed  
synchronous static RAM designed to provide a burstable,  
high-performance memory for high speed networking and  
communication applications. It is organized as 131,072  
words by 32 bits or 36 bits, fabricated with ISSI's advanced  
CMOStechnology.Thedeviceintegratesa2-bitburstcounter,  
high-speed SRAM core, and high-drive capability outputs into  
a single monolithic circuit. All synchronous inputs pass  
through registers controlled by a positive-edge-triggered  
single clock input.  
• Fast access times: 7.5 ns, 8 ns, 8.5 ns, 10 ns,  
and 12 ns  
• Internal self-timed write cycle  
• Individual Byte Write Control and Global Write  
• Clock controlled, registered address, data  
inputs and control signals  
• Pentium™ or linear burst sequence control  
using MODE input  
• Three chip enables for simple depth expansion  
and address pipelining  
Write cycles are internally self-timed and are initiated by the  
rising edge of the clock input. Write cycles can be from one to  
four bytes wide as controlled by the write control inputs.  
• Common data inputs and data outputs  
Separate byte enables allow individual bytes to be written.  
BW1 controls DQa, BW2 controls DQb, BW3 controls DQc,  
BW4 controls DQd, conditioned by BWE being LOW. A LOW  
on GW input would cause all bytes to be written.  
• JEDEC 100-Pin TQFP and  
119-pin PBGA package  
• Single +3.3V +10%, –5% power supply  
• Power-down snooze mode  
Bursts can be initiated with either ADSP (Address Status  
Processor) or ADSC (Address Status Cache Controller) input  
pins.Subsequentburstaddressescanbegeneratedinternally  
and controlled by the ADV (burst address advance) input pin.  
The mode pin is used to select the burst sequence order,  
Linear burst is achieved when this pin is tied LOW. Interleave  
burst is achieved when this pin is tied HIGH or left floating.  
FAST ACCESS TIME  
Symbol  
tKQ  
Parameter  
Clock Access Time  
Cycle Time  
7.5  
7.5  
8.5  
117  
8
8
10  
100  
8.5  
8.5  
11  
10  
10  
15  
66  
12  
12  
15  
66  
Units  
ns  
ns  
tKC  
Frequency  
90  
MHz  
ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any  
errors which may appear in this publication. © Copyright 2001, Integrated Silicon Solution, Inc.  
Integrated Silicon Solution, Inc. — 1-800-379-4774  
1
Rev. A  
04/17/01  

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