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IS61LV12816-15LQ PDF预览

IS61LV12816-15LQ

更新时间: 2024-11-23 22:48:03
品牌 Logo 应用领域
美国芯成 - ISSI /
页数 文件大小 规格书
11页 90K
描述
128K x 16 HIGH-SPEED CMOS STATIC RAM WITH 3.3V SUPPLY

IS61LV12816-15LQ 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:QFP包装说明:LQFP, QFP44,.47SQ,32
针数:44Reach Compliance Code:not_compliant
ECCN代码:3A991.B.2.AHTS代码:8542.32.00.41
风险等级:5.83最长访问时间:15 ns
其他特性:TTL AND CMOS COMPATIBLE INTERFACE LEVELSI/O 类型:COMMON
JESD-30 代码:S-PQFP-G44JESD-609代码:e0
长度:10 mm内存密度:2097152 bit
内存集成电路类型:STANDARD SRAM内存宽度:16
功能数量:1端子数量:44
字数:131072 words字数代码:128000
工作模式:ASYNCHRONOUS最高工作温度:70 °C
最低工作温度:组织:128KX16
输出特性:3-STATE封装主体材料:PLASTIC/EPOXY
封装代码:LQFP封装等效代码:QFP44,.47SQ,32
封装形状:SQUARE封装形式:FLATPACK, LOW PROFILE
并行/串行:PARALLEL峰值回流温度(摄氏度):NOT SPECIFIED
电源:3.3 V认证状态:Not Qualified
座面最大高度:1.6 mm最大待机电流:0.01 A
最小待机电流:3 V子类别:SRAMs
最大压摆率:0.09 mA最大供电电压 (Vsup):3.63 V
最小供电电压 (Vsup):2.97 V标称供电电压 (Vsup):3.3 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:GULL WING端子节距:0.8 mm
端子位置:QUAD处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:10 mmBase Number Matches:1

IS61LV12816-15LQ 数据手册

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®
IS61LV12816  
128K x 16 HIGH-SPEED CMOS STATIC RAM  
WITH 3.3V SUPPLY  
ISSI  
NOVEMBER 2000  
FEATURES  
DESCRIPTION  
The ISSI IS61LV12816 is a high-speed, 2,097,152-bit static  
RAM organized as 131,072 words bꢂ 16 bits. It is fabricated  
ꢁsingISSI'shigh-performanceCMOStechnologꢂ. Thishighlꢂ  
reliable process coꢁpled with innovative circꢁit design  
techniqꢁes, ꢂields access times as fast as 8 ns with low power  
consꢁmption.  
• High-speed access time: 8, 10, 12, and 15 ns  
• CMOS low power operation  
• TTL and CMOS compatible interface levels  
• Single 3.3V 10ꢀ power sꢁpplꢂ  
• Fꢁllꢂ static operation: no clock or refresh  
reqꢁired  
When CE is HIGH (deselected), the device assꢁmes a  
standbꢂ mode at which the power dissipation can be redꢁced  
down with CMOS inpꢁt levels.  
• Three state oꢁtpꢁts  
• Data control for ꢁpper and lower bꢂtes  
• Indꢁstrial temperatꢁre available  
EasmemorexpansionisprovidedbsingChipEnableand  
Oꢁtpꢁt Enable inpꢁts, CE and OE. The active LOW Write  
Enable (WE) controls both writing and reading of the memorꢂ.  
A data bꢂte allows Upper Bꢂte (UB) and Lower Bꢂte (LB)  
access.  
The IS61LV12816 is packaged in the JEDEC standard 44-pin  
400-mil SOJ, 44-pin TSOP, 44-pin LQFP, and 48-pin mini  
BGA (6mm x 8mm).  
FUNCTIONAL BLOCK DIAGRAM  
128K x 16  
MEMORY ARRAY  
A0-A16  
DECODER  
VCC  
GND  
I/O0-I/O7  
Lower Byte  
I/O  
DATA  
COLUMN I/O  
CIRCUIT  
I/O8-I/O15  
Upper Byte  
CE  
OE  
WE  
CONTROL  
CIRCUIT  
UB  
LB  
ISSI reserves the right to make changes to its prodꢁcts at anꢂ time withoꢁt notice in order to improve design and sꢁpplꢂ the best possible prodꢁct. We assꢁme no responsibilitꢂ for anꢂ errors  
which maꢂ appear in this pꢁblication. © Copꢂright 2000, Integrated Silicon Solꢁtion, Inc.  
Integrated Silicon Solution, Inc. — 11--880000--337799--44777744  
1
Rev. A  
11/30/00  

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