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IS61LV12816-8K PDF预览

IS61LV12816-8K

更新时间: 2024-11-23 22:48:03
品牌 Logo 应用领域
矽成 - ICSI /
页数 文件大小 规格书
11页 146K
描述
128K x 16 HIGH-SPEED CMOS STATIC RAM

IS61LV12816-8K 技术参数

是否Rohs认证: 不符合生命周期:Transferred
包装说明:SOJ, SOJ44,.44Reach Compliance Code:unknown
风险等级:5.86最长访问时间:8 ns
I/O 类型:COMMONJESD-30 代码:R-PDSO-J44
JESD-609代码:e0内存密度:2097152 bit
内存集成电路类型:STANDARD SRAM内存宽度:16
端子数量:44字数:131072 words
字数代码:128000工作模式:ASYNCHRONOUS
最高工作温度:70 °C最低工作温度:
组织:128KX16输出特性:3-STATE
封装主体材料:PLASTIC/EPOXY封装代码:SOJ
封装等效代码:SOJ44,.44封装形状:RECTANGULAR
封装形式:SMALL OUTLINE并行/串行:PARALLEL
电源:3.3 V认证状态:Not Qualified
最大待机电流:0.01 A最小待机电流:3 V
子类别:SRAMs最大压摆率:0.22 mA
标称供电电压 (Vsup):3.3 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子面层:Tin/Lead (Sn/Pb)端子形式:J BEND
端子节距:1.27 mm端子位置:DUAL
Base Number Matches:1

IS61LV12816-8K 数据手册

 浏览型号IS61LV12816-8K的Datasheet PDF文件第2页浏览型号IS61LV12816-8K的Datasheet PDF文件第3页浏览型号IS61LV12816-8K的Datasheet PDF文件第4页浏览型号IS61LV12816-8K的Datasheet PDF文件第5页浏览型号IS61LV12816-8K的Datasheet PDF文件第6页浏览型号IS61LV12816-8K的Datasheet PDF文件第7页 
IS61LV12816  
128K x 16 HIGH-SPEED CMOS STATIC RAM  
WITH 3.3V SUPPLY  
FEATURES  
DESCRIPTION  
The ICSI IS61LV12816 is a high-speed, 2,097,152-bit static  
RAM organized as 131,072 words by 16 bits. It is fabricated  
using ICSI's high-performance CMOS technology. This highly  
reliable process coupled with innovative circuit design  
techniques, yields access times as fast as 8 ns with low power  
consumption.  
• High-speed access time: 8, 10, 12, and 15 ns  
• CMOS low power operation  
• TTL and CMOS compatible interface levels  
• Single 3.3V + 10%power supply  
• Fully static operation: no clock or refresh  
required  
When CE is HIGH (deselected), the device assumes a standby  
mode at which the power dissipation can be reduced down with  
CMOS input levels.  
• Three state outputs  
• Data control for upper and lower bytes  
• Industrial temperature available  
Easy memory expansion is provided by using Chip Enable and  
Output Enable inputs, CE and OE. The active LOW Write  
Enable (WE) controls both writing and reading of the memory.  
A data byte allows Upper Byte (UB) and Lower Byte (LB)  
access.  
The IS61LV12816 is packaged in the JEDEC standard 44-pin  
400mil SOJ, 44-pin 400mil TSOP-2, and 48-pin 6*8mm TF-  
BGA.  
FUNCTIONAL BLOCK DIAGRAM  
128K x 16  
MEMORY ARRAY  
A0-A16  
DECODER  
VCC  
GND  
I/O0-I/O7  
Lower Byte  
I/O  
DATA  
COLUMN I/O  
CIRCUIT  
I/O8-I/O15  
Upper Byte  
CE  
OE  
WE  
CONTROL  
CIRCUIT  
UB  
LB  
ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors  
which may appear in this publication. © Copyright 2000, Integrated Circuit Solution, Inc.  
Integrated Circuit Solution, Inc.  
SR023_0C  
1

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