5秒后页面跳转
捷配首页

Datasheet > IS61DDB21M18A-300M3
IS61DDB21M18A-300M3 PDF预览

IS61DDB21M18A-300M3

更新时间： 2024-11-18 14:42:55
品牌 Logo 应用领域
美国芯成 - ISSI 时钟双倍数据速率静态存储器内存集成电路
页数 文件大小 规格书
29页 453K
描述
DDR SRAM, 1MX18, 0.45ns, CMOS, PBGA165, 15 X 17 MM, 1.40 MM HEIGHT, LFBGA-165

阅读下载

中文翻译

获取价格

IS61DDB21M18A-300M3 技术参数

是否无铅： 含铅是否Rohs认证： 不符合
生命周期：Active零件包装代码：BGA
包装说明：LBGA, BGA165,11X15,40针数：165
Reach Compliance Code：compliantECCN代码：3A991.B.2.A
HTS代码：8542.32.00.41风险等级：5.3
最长访问时间：0.45 ns其他特性：PIPELINED ARCHITECTURE
最大时钟频率 (fCLK)：300 MHzI/O 类型：COMMON
JESD-30 代码：R-PBGA-B165JESD-609代码：e0
长度：17 mm内存密度：18874368 bit
内存集成电路类型：DDR SRAM内存宽度：18
功能数量：1端子数量：165
字数：1048576 words字数代码：1000000
工作模式：SYNCHRONOUS最高工作温度：70 °C
最低工作温度：组织：1MX18
输出特性：3-STATE封装主体材料：PLASTIC/EPOXY
封装代码：LBGA封装等效代码：BGA165,11X15,40
封装形状：RECTANGULAR封装形式：GRID ARRAY, LOW PROFILE
并行/串行：PARALLEL峰值回流温度（摄氏度）：NOT SPECIFIED
电源：1.5/1.8,1.8 V认证状态：Not Qualified
座面最大高度：1.4 mm最大待机电流：0.28 A
最小待机电流：1.7 V子类别：SRAMs
最大压摆率：0.55 mA最大供电电压 (Vsup)：1.89 V
最小供电电压 (Vsup)：1.71 V标称供电电压 (Vsup)：1.8 V
表面贴装：YES技术：CMOS
温度等级：COMMERCIAL端子面层：TIN LEAD
端子形式：BALL端子节距：1 mm
端子位置：BOTTOM处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：15 mmBase Number Matches：1

IS61DDB21M18A-300M3 数据手册

 浏览型号IS61DDB21M18A-300M3的Datasheet PDF文件第2页浏览型号IS61DDB21M18A-300M3的Datasheet PDF文件第3页浏览型号IS61DDB21M18A-300M3的Datasheet PDF文件第4页浏览型号IS61DDB21M18A-300M3的Datasheet PDF文件第5页浏览型号IS61DDB21M18A-300M3的Datasheet PDF文件第6页浏览型号IS61DDB21M18A-300M3的Datasheet PDF文件第7页 
IS61DDB21M18A  
IS61DDB251236A  
1Mx18, 512Kx36  
ADVANCED INFORMATION  
JULY 2012  
18Mb DDR-II (Burst 2) CIO SYNCHRONOUS SRAM  
FEATURES  
DESCRIPTION  
The 18Mb IS61DDB251236A and IS61DDB21M18A are  
synchronous, high-performance CMOS static random access  
memory (SRAM) devices. These SRAMs have a common I/O  
bus. The rising edge of K clock initiates the read/write  
operation, and all internal operations are self-timed. Refer to  
the Timing Reference Diagram for Truth Table for a  
description of the basic operations of these DDR-II (Burst of  
2) CIO SRAMs.  
512Kx36 and 1Mx18 configuration available.  
On-chip delay-locked loop (DLL) for wide data valid  
window.  
Common I/O read and write ports.  
Synchronous pipeline read with self-timed late write  
operation.  
Double Data Rate (DDR) interface for read and  
write input ports.  
Read and write addresses are registered on alternating rising  
edges of the K clock. Reads and writes are performed in  
double data rate.  
Fixed 2-bit burst for read and write operations.  
Clock stop support.  
The following are registered internally on the rising edge of  
the K clock:  
Two input clocks (K and K#) for address and control  
registering at rising edges only.  
Read/write address  
Read enable  
Write enable  
Byte writes for first burst address  
Data-in for first burst address  
Two input clocks (C and C#) for data output control.  
Two echo clocks (CQ and CQ#) that are delivered  
simultaneously with data.  
+1.8V core power supply and 1.5V to 1.8V VDDQ,  
used with 0.75V to 0.9V VREF.  
The following are registered on the rising edge of the K#  
clock:  
HSTL input and output interface.  
Registered addresses, write and read controls, byte  
writes, data in, and data outputs.  
Byte writes for second burst address  
Data-in for second burst address  
Full data coherency.  
Boundary scan using limited set of JTAG 1149.1  
functions.  
Byte writes can change with the corresponding data-in to  
enable or disable writes on a per-byte basis. An internal write  
buffer enables the data-ins to be registered one cycle after  
the write address. The first data-in burst is clocked one cycle  
later than the write command signal, and the second burst is  
timed to the following rising edge of the K# clock.  
Byte write capability.  
Fine ball grid array (FBGA) package:  
13mmx15mm and 15mmx17mm body size  
165-ball (11 x 15) array  
During the burst read operation, the data-outs from the first  
bursts are updated from output registers of the second rising  
edge of the C# clock (starting one and half cycles later after  
read command). The data-outs from the second bursts are  
updated with the third rising edge of the C clock. The K and  
K# clocks are used to time the data-outs whenever the C and  
C# clocks are tied high.  
Programmable impedance output drivers via 5x  
user-supplied precision resistor.  
The device is operated with a single +1.8V power supply and  
is compatible with HSTL I/O interfaces.  
Copyright © 2012 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time  
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to  
obtain the latest version of this device specification before relying on any published information and before placing orders for products.  
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can  
reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such  
applications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that:  
a.) the risk of injury or damage has been minimized;  
b.) the user assume all such risks; and  
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances  
Integrated Silicon Solution, Inc.- www.issi.com  
Rev. 00A  
1
7/5/2012  
1234567...29

中文翻译

下载PDF

与IS61DDB21M18A-300M3相关器件

型号 品牌 获取价格 描述 数据表
IS61DDB21M18A-300M3I ISSI

获取价格

 		DDR SRAM, 1MX18, 0.45ns, CMOS, PBGA165, 15 X 17 MM, 1.40 MM HEIGHT, LFBGA-165
IS61DDB21M18A-300M3L ISSI

获取价格

 		DDR SRAM, 1MX18, 0.45ns, CMOS, PBGA165, 15 X 17 MM, 1.40 MM HEIGHT, LEAD FREE, LFBGA-165
IS61DDB21M18A-333M3LI ISSI

获取价格

 		DDR SRAM, 1MX18, 0.45ns, CMOS, PBGA165, 15 X 17 MM, 1.40 MM HEIGHT, LEAD FREE, LFBGA-165
IS61DDB21M36-250M3 ISSI

获取价格

 		36 Mb (1M x 36 & 2M x 18) DDR-II (Burst of 2) CIO Synchronous SRAMs
IS61DDB21M36-250M3L ISSI

获取价格

 		1MX36 DDR SRAM, 0.35ns, PBGA165, 15 X 17 MM, 1 MM PITCH, LEAD FREE, FBGA-165
IS61DDB21M36-250M3LI ISSI

获取价格

 		IC,SYNC SRAM,DDR,1MX36,CMOS,BGA,165PIN,PLASTIC,
IS61DDB21M36A ISSI

获取价格

 		Clock stop support
IS61DDB22M18 ISSI

获取价格

 		36 Mb (1M x 36 & 2M x 18) DDR-II (Burst of 2) CIO Synchronous SRAMs
IS61DDB22M18-250M3 ISSI

获取价格

 		36 Mb (1M x 36 & 2M x 18) DDR-II (Burst of 2) CIO Synchronous SRAMs
IS61DDB22M18A ISSI

获取价格

 		Clock stop support

与IS61DDB21M18A-300M3相关文章

您还可以找


热门产品
PCB打样/小批量
铝基板
BOM智能配单
PCBA制造
钣金
精密CNC
模具注塑
薄膜开关
精选活动
PCBA打样特惠
四六层板品质升级
铝基板品质升级
一体化电子制造
DFM下载
服务支持
企业认证
产品展示
工厂展示
工艺能力
积分商城
关于捷配
捷配简介
企业文化
公司动态
人才招聘
联系我们
帮助中心
下单流程
付款流程
开票流程
常见问题
全球PCB制造服务专线 400-613-0088

工作时间：9:00-21:00

CEO邮箱：ceo@jiepei.com

投诉邮箱：tousu@jiepei.com

捷配网-微信公众号 微信公众号
捷配网-微信公众号 抖音公众号
资质认证：
合作快递：
支付方式：
Copyright © 2024 Jiepei.com Inc. All Rights Reserved. 版权所有:杭州捷配信息科技有限公司 浙公网安备 33010502006866号 浙ICP备10014259号-119 营业执照ICP证