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IS61DDB22M36-300M3L PDF预览

IS61DDB22M36-300M3L

更新时间： 2024-11-18 05:39:35
品牌 Logo 应用领域
美国芯成 - ISSI 存储内存集成电路静态存储器双倍数据速率时钟
页数 文件大小 规格书
25页 601K
描述
72 Mb (2M x 36 & 4M x 18) DDR-II (Burst of 2) CIO Synchronous SRAMs

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中文翻译

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IS61DDB22M36-300M3L 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Obsolete零件包装代码：BGA
包装说明：LBGA, BGA165,11X15,40针数：165
Reach Compliance Code：compliantECCN代码：3A991.B.2.A
HTS代码：8542.32.00.41风险等级：5.68
最长访问时间：0.35 ns其他特性：PIPELINED ARCHITECTURE
最大时钟频率 (fCLK)：300 MHzI/O 类型：COMMON
JESD-30 代码：R-PBGA-B165JESD-609代码：e1
长度：17 mm内存密度：75497472 bit
内存集成电路类型：DDR SRAM内存宽度：36
湿度敏感等级：3功能数量：1
端子数量：165字数：2097152 words
字数代码：2000000工作模式：SYNCHRONOUS
最高工作温度：70 °C最低工作温度：
组织：2MX36输出特性：3-STATE
封装主体材料：PLASTIC/EPOXY封装代码：LBGA
封装等效代码：BGA165,11X15,40封装形状：RECTANGULAR
封装形式：GRID ARRAY, LOW PROFILE并行/串行：PARALLEL
峰值回流温度（摄氏度）：260电源：1.5/1.8,1.8 V
认证状态：Not Qualified座面最大高度：1.4 mm
最小待机电流：1.7 V子类别：SRAMs
最大压摆率：0.6 mA最大供电电压 (Vsup)：1.89 V
最小供电电压 (Vsup)：1.71 V标称供电电压 (Vsup)：1.8 V
表面贴装：YES技术：CMOS
温度等级：COMMERCIAL端子面层：Tin/Silver/Copper (Sn/Ag/Cu)
端子形式：BALL端子节距：1 mm
端子位置：BOTTOM处于峰值回流温度下的最长时间：10
宽度：15 mmBase Number Matches：1

IS61DDB22M36-300M3L 数据手册

 浏览型号IS61DDB22M36-300M3L的Datasheet PDF文件第2页浏览型号IS61DDB22M36-300M3L的Datasheet PDF文件第3页浏览型号IS61DDB22M36-300M3L的Datasheet PDF文件第4页浏览型号IS61DDB22M36-300M3L的Datasheet PDF文件第5页浏览型号IS61DDB22M36-300M3L的Datasheet PDF文件第6页浏览型号IS61DDB22M36-300M3L的Datasheet PDF文件第7页 
72 Mb (2M x 3  
.
6 & 4M x 18)  
DDR-II (Burst of 2) CIO Synchronous SRAMs  
November 2009  
• Two echo clocks (CQ and CQ) that are delivered  
simultaneously with data.  
Features  
• 2M x 36 or 4M x 18.  
• +1.8V core power supply and 1.5, 1.8V VDDQ  
used with 0.75, 0.9V VREF  
,
• On-chip delay-locked loop (DLL) for wide data  
valid window.  
.
• HSTL input and output levels.  
• Common data input/output bus.  
• Registered addresses, write and read controls,  
byte writes, data in, and data outputs.  
• Synchronous pipeline read with self-timed late  
write operation.  
• Full data coherency.  
• Double data rate (DDR-II) interface for read and  
• Boundary scan using limited set of JTAG 1149.1  
functions.  
write input ports.  
• Fixed 2-bit burst for read and write operations.  
• Clock stop support.  
• Byte write capability.  
• Fine ball grid array (FBGA) package  
- 15mm x 17mm body size  
- 1mm pitch  
• Two input clocks (K and K) for address and con-  
trol registering at rising edges only.  
• Two input clocks (C and C) for data output con-  
trol.  
- 165-ball (11 x 15) array  
• Programmable impedance output drivers via 5x  
user-supplied precision resistor.  
Industrial temperature available upon request.  
•
Description  
The 72Mb IS61DDB22M36 and  
The following are registered on the rising edge of  
the K clock:  
IS61DDB24M18 are synchronous, high-perfor-  
mance CMOS static random access memory  
(SRAM) devices. These SRAMs have a common I/O  
bus. The rising edge of K clock initiates the  
read/write operation, and all internal operations are  
self-timed.  
•
y
B te writes  
• Data-in for second burst addresses  
Byte writes can change with the corresponding data-  
in to enable or disable writes on a per-byte basis. An  
internal write buffer enables the data-ins to be regis-  
tered one cycle later than the write address. The first  
data-in burst is clocked with the rising edge of the  
next K clock, and the second burst is timed to the  
following rising edge of the K clock.  
Refer to the Timing Reference Diagram for Truth  
Table on page 8 for a description of the basic opera-  
tions of these DDR-II (Burst of 2) CIO SRAMs.  
The input addresses are registered on all rising  
edges of the K clock. The DQ bus operates at  
double data rate for reads and writes. The following  
are registered internally on the rising edge of the K  
clock:  
During the burst read operation, at the first burst the  
data-outs are updated from output registers off the  
second rising edge of the C clock (1.5 cycles later).  
At the second burst, the data-outs are updated with  
the third rising edge of the corresponding C clock  
(see page 9). The K and K clocks are used to time  
the data-outs whenever the C and C clocks are tied  
high.  
• Read and write addresses  
• Address load  
• Read/write enable  
y
B te writes  
• Data-in  
The device is operated with a single +1.8V power  
supply and is compatible with HSTL I/O interfaces.  
Integrated Silicon Solution, Inc.  
1
Rev. B  
11/10/09  
1234567...25

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与IS61DDB22M36-300M3L相关器件

型号 品牌 获取价格 描述 数据表
IS61DDB22M36-300M3LI ISSI

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 		72 Mb (2M x 36 & 4M x 18) DDR-II (Burst of 2) CIO Synchronous SRAMs
IS61DDB22M36A ISSI

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 		Common I/O read and write ports
IS61DDB22M36A-300B4LI ISSI

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 		DDR SRAM, 2MX36, 0.45ns, CMOS, PBGA165, 13 X 15 MM, 1.40 MM HEIGHT, LEAD FREE, LFBGA-165
IS61DDB22M36A-300M3L ISSI

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 		DDR SRAM, 2MX36, 0.45ns, CMOS, PBGA165, 15 X 17 MM, 1.40 MM HEIGHT, LEAD FREE, LFBGA-165
IS61DDB24M18-250M3 ISSI

获取价格

 		72 Mb (2M x 36 & 4M x 18) DDR-II (Burst of 2) CIO Synchronous SRAMs
IS61DDB24M18-250M3L ISSI

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 		72 Mb (2M x 36 & 4M x 18) DDR-II (Burst of 2) CIO Synchronous SRAMs
IS61DDB24M18-300M3 ISSI

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 		72 Mb (2M x 36 & 4M x 18) DDR-II (Burst of 2) CIO Synchronous SRAMs
IS61DDB24M18-300M3L ISSI

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 		72 Mb (2M x 36 & 4M x 18) DDR-II (Burst of 2) CIO Synchronous SRAMs
IS61DDB24M18A ISSI

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 		Common I/O read and write ports
IS61DDB251236A ISSI

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 		Fixed 2-bit burst for read and write operations

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